In this letter, a new asynchronous Re-Order Buffer (ROB) with fully distributed control is proposed for an asynchronous on-chip bus. Due to the fully distributed control by each dedicated controller, the proposed ROB has high modularity and scalability. Simulation results show that the proposed asynchronous ROB can operate on an asynchronous on-chip bus of 2.01 Gbit/s throughput and 0.232 nJ power consumption per bus transaction.

Since the inception of Globally Asynchronous Locally Synchronous (GALS) VLSI design, GALS has been considered a promising design technique for multi-clock-domain System-on-Chip (SoC). Among the handshake protocols available for SoC design, delay insensitive (DI) handshake protocol is becoming a core technology, since it facilitates robust data transfer regardless of wire delay variation. In this paper, a new data encoding scheme Differential Value Encoding (DVE) is proposed for two-phase 1-of-N DI handshake protocol. Compared with the conventional data encoding method, the proposed scheme effectively reduces the crosstalk effect on wires sending sequentially increasing data patterns, resulting in reduction of the data transfer time. Simulation results with SPEC CPU 2000 benchmarks and sequentially increasing data pattern reveal that the DVE scheme can reduce the crosstalk effect by tens of percentage and significantly decrease the data transfer time.

In this paper, we develop asymptotic analysis and simulation models to better understand the characteristics of performance and energy consumption in a multi-core processor design in which dynamic voltage scaling is used. Our asymptotic model is derived using Amdahl's law, Rent's rule and power equations to derive the optimum number of cores and their voltage levels. Our model can predict the possible impact of different multi-core processor configurations on the performance and energy consumption for given workload characteristics (e.g. available parallelism) and process technology parameters (e.g. ratios of dynamic and static energies to total energy). Through the asymptotic analysis and optimization based on the models, we can observe an asymptotic relationship between design parameters such as "the number of cores," "core size" and "voltage scaling strategies" of a multi-core architecture with regards to performance and energy consumption at an initial phase of the design.

The cryptographic algorithm called INCrypt32 is a MAC algorithm to authenticate participants, RFID cards and readers, in HID Global's iCLASS systems. HID's iCLASS cards are widely used contactless smart cards for physical access control. Although INCrypt32 is a heart of the security of HID's iCLASS systems, its security has not been evaluated yet since the specification has not been open to public. In this paper, we reveal the specification of INCrypt32 by reverse-engineering iCLASS cards and investigate the security of INCrypt32 with respect to the cryptographic sense. This result is the first work to describe the details of INCrypt32 and the possibility of a secret key (64-bit) recovery in our attack environments. 242 MAC queries are required in the real environment using secure communication protocols. But the required number of MAC queries decreases to 218 if MAC quires for chosen messages with arbitrary length can be requested.

A multiple-issue on-chip bus of a layered architecture in a Globally Asynchronous Locally Synchronous (GALS) design style, supporting in-order/out-of-order completion, is proposed in this letter. The throughput of the proposed on-chip bus is increased by 31.3% and 34.3%, while power consumption overhead is only 6.76% and 3.98%, respectively, as compared to an asynchronous single-issue on-chip bus.

This paper presents a new asynchronous multiplier. The original array structure is divided into two asymmetric arrays, called an upper array and a lower array. For the lower array, Left to Right scheme is applied to take advantage of a fast computation and low power consumption as well. Simulation results show that the proposed multiplier has 40% of performance improvement with a relatively lower power consumption. The multiplier has been implemented in a CMOS 0.35 µm technology and proved functionally correct.