IEICE TRANSACTIONS on Fundamentals
A Parallel Flop Synchronizer and the Handshake Interface for Bridging Asynchronous Domains
Summary :
Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data to the clock domain. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed scheme can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level. All designs have been implemented in a 0.25 µm CMOS technology to verify performance analysis of the proposed synchronization.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3166-3173
- Publication Date
- 2004/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis
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Suk-Jin KIM, Jeong-Gun LEE, Kiseon KIM, "A Parallel Flop Synchronizer and the Handshake Interface for Bridging Asynchronous Domains" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 12, pp. 3166-3173, December 2004, doi: .
Abstract: Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data to the clock domain. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed scheme can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level. All designs have been implemented in a 0.25 µm CMOS technology to verify performance analysis of the proposed synchronization.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3166/_p
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@ARTICLE{e87-a_12_3166,
author={Suk-Jin KIM, Jeong-Gun LEE, Kiseon KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Parallel Flop Synchronizer and the Handshake Interface for Bridging Asynchronous Domains},
year={2004},
volume={E87-A},
number={12},
pages={3166-3173},
abstract={Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data to the clock domain. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed scheme can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level. All designs have been implemented in a 0.25 µm CMOS technology to verify performance analysis of the proposed synchronization.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A Parallel Flop Synchronizer and the Handshake Interface for Bridging Asynchronous Domains
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3166
EP - 3173
AU - Suk-Jin KIM
AU - Jeong-Gun LEE
AU - Kiseon KIM
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data to the clock domain. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed scheme can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level. All designs have been implemented in a 0.25 µm CMOS technology to verify performance analysis of the proposed synchronization.
ER -
English
