In this paper, a novel CMOS defuzzification circuit using dual-output current conveyors (DO-CCII) is introduced. The behaviour of the proposed circuit has been verified with PSPICE using the models for 1.2 µm MIETEC CMOS process. The proposed circuit offers high-speed operation and high accuracy because of using second generation current conveyors (CCII). The designed circuit is suitable for fuzzy logic controllers using center of gravity (COG) defuzzification method.

A readout circuit involving new two step current mode background suppression is studied for 2-dimensional long wavelength infrared focal plane arrays (LWIR FPA's). Buffered direct injection (BDI) and feedback amplifier structure are adopted for input circuit and background suppression circuit, respectively. The pixel circuit is simple and has very small skimming error less than 0.1%. Enough calibration range over 50% as well as long integration time over 1.75 ms can be obtained using this readout circuit.

In this paper, we propose a new method which makes transient simulation faster for the circuit including both nonlinear and linear elements. First, the method for generating the projection matrix with Krylov-subspace technique is described. The order of the circuit equation is reduced by congruence transformation with the projection matrix. Next, we suggest a method which can calculate the reduced Jacobian matrix directly in each Newton-Raphson iteration. Since this technique does not need to calculate the original size of Jacobian matrix, the calculation cost is reduced drastically. Therefore, efficient circuit simulation can be achieved. Finally, our method is applied to some example circuits and the validity of the nonlinear circuit reduction technique is verified.

First we introduce the high-frequency equivalent circuit model of the Fine Pitched Ball Grid Array (FPBGA) bonding for frequencies up to 20 GHz. The lumped circuit model of the FPBGA bonding was extracted based on S-parameters measurement and subsequent fitting of the model parameters. The test packages, which contain probing pads, coplanar waveguides and FPBGA ball bonding, were fabricated and measured. The suggested π-model of the FPBGA bonding consists of self-inductor, self-capacitor, and self-resistor components. From the extracted model, a solder ball of 350 µm diameter and 800 µm ball pitch has less than 0.08 nH self-inductance, 0.40 pF self capacitance, and about 10 mΩ self-resistance. In addition, the mutual capacitance caused by the presence of the adjacent bonding balls is included in the model. The FPBGA solder ball bonding has less than 1.5 dB insertion loss up to 20 GHz, and it causes negligible delay time in digital signal transmission. The extracted circuit model of FPBGA bonding is useful in design and performance simulation of advanced packages, which use FPBGA bonding.

Subcircuits designed for integrated silicon DCS1800/ PCS1900 base station receivers have been reconfigured into hybrid and single-chip Doppler radar transceivers. Radar chips have been fully integrated in 0.25 µm silicon CMOS and BiCMOS processes. These chips have been used to monitor heart and respiration activity without contact, and they have successfully detected heartbeat and respiration rate up to 1 m from the subject. This monitoring device may be useful in home monitoring, continuous monitoring, and physiological research.

A Power on Reset signal generation circuit referencing threshold voltage without standby current consumption has been proposed. The POR signal is generated when supply voltage is larger than the sum of threshold voltages of N- and P-MOSFET.

An output load VSWR (voltage standing wave ratio) protection circuit for SiGe power amplifiers (PA) is presented by using the relatively low collector-emitter avalanche breakdown characteristic of SiGe HBT. Unlike the conventional diode-type switch, the new protection circuit completely eliminates the undesirable dc leakage current during the normal operation of the PA. Simulations and measurements show the proposed protection circuit enhances the ruggedness of the PA at harsh operating condition while it imposes only minor performance degradation at normal operating condition.

A novel method is presented to the symbolic computation of Noise Figure (NF) of transistor circuits. Several computationally efficient macromodels of BJTs and MOSFETs by using nullors, are introduced. To demonstrate the suitability of the proposed method, the fully-symbolic expression of NF of a CMOS current-mirror is computed, and the total output noise-voltage is compared with HSPICE simulations. The calculated NF and the simulated noise are in good agreement. Finally, the method is extended to compute NF of a CMOS translinear circuit biased in weak inversion.

Subgraph isomorphism problems have various important applications, while generally being NP-complete. Though Ullmann and Konishi proposed the custom circuit designs to accelerate subgraph isomorphism problem, they require many hardware resources for large problems. This study describes the design of data-dependent circuits for subgraph isomorphism problem with evaluation results on an actual FPGA platform. Data-dependent circuits are logic circuits specialized in specific input data. Such circuits are smaller and faster than the original circuit, although it is not reusable and involves circuit generation for each input. In the present study, the circuits were implemented on Xilinx XC2V3000 FPGA, and they successfully operated at a clock frequency 25 MHz. In the case of graphs with 16 vertices, the average execution time is about 7.0% of the software executed on an up-to-date microprocessor (Athlon XP 2600+ of 2.1 GHz clock). Even if the circuit generation time is included, data-dependent circuits are about 14.4 times faster than the software (for random graphs with 16 vertices). This performance advantage becomes larger for larger graphs. Two algorithms (Ullmann's and Konishi's) were examined, and the data-dependent approach was found to be equally effective for both algorithms. We also examined two types of input graph sets, and found that the data-dependent approach shows advantage in both cases.

In the optimum design of AC contactors, it is necessary to analyze the dynamic behavior. Moreover, movable contacts and core bounce have remarkable effect on the lifetime of contactors. A set of differential equations describes the coupling of the electric circuit, electromagnetic field and mechanical system taking account into bounce and the influence of friction. With virtual prototyping technology, the dynamic behavior, especially for contacts bounce, has been investigated according to different electrical circuit parameters. Two approaches are introduced to solve electromagnetic parameters. Based on 3D finite element static nonlinear analysis, the flux linkage and electromagnetic force can be evaluated with different air gap and exciting current for larger gap. In addition, concerning to the shading coil for smaller gap, magnetic circuit can facilitate the calculation. The validity of the proposed method is confirmed by experiments.

Common-mode excitation caused by an imperfect ground plane on a printed circuit board (PCB) has been conventionally explained with the 'current driven' scheme, in which the common-mode current is driven by the ground voltage across the unintentional inductance of the ground plane. We have developed an alternative method for estimating common-mode excitation that is driven by the difference of the common-mode voltages for two connected transmission lines. A parameter called current division factor (CDF) that represents the degree of imbalance of a transmission line explains the common-mode voltage. In this paper, we calculate the CDF with two-dimensional (2-D) static electric field analysis by using the boundary element method (BEM) for asymmetric transmission lines with an arbitrary cross-section. The proposed 2-D method requires less time than three-dimensional simulations. The EMI increase due to a signal line being close to the edge of the ground pattern was evaluated through CDF calculation. The estimated increase agreed well--within 2 dB--with the measured one.

The current paper presents the design, analysis, and implementation of a low-profile resonant dc-to-dc converter that utilizes a coreless printed circuit board transformer as a substitute for the conventional magnetic core-based transformer. A prototype series resonant converter, fabricated in a 40 mm80 mm area with a 4 mm thickness while achieving the maximum efficiency of 85% at a 58 W output power, is used as an example to address the theoretical and practical issues involved in the design, analysis, and implementation of a PCB transformer-based low-profile dc-to-dc converter.

Design points and the results seen in the development of a dynamically reconfigurable logic LSI, PCA-2, are described. PCA-2 enables the realization of flexible parallel processing based on the autonomous reconfiguration of logic circuits. To realize this feature, we introduce an asynchronous circuit design and a homogeneous cell array structure. PCA-2 represents an advance on the earlier LSI, PCA-1. Cutting edge CMOS technology is used to realize the structural merits of PCA hardware. Compared to PCA-1, PCA-2 offers 16 times greater integration level for programmable logic. Due to miniaturization and design refinement, PCA-2 provides a 6-fold increase in the circuit frequency of the configuration controller and a 3-fold increase in the operating frequency of the programmable logic. The results gained confirm the effects of refinement and the suitability of our architecture for device miniaturization.

The effect of the structure with difference on cross-section for the enlarged models that simulates signal transmission line (STL) in the magnetic head of HDD is discussed. The experimental results suggested that strip and shield structure are effective for suppression of EMI.

A novel high speed, low voltage BiCMOS tristate buffer is presented and its performance characteristics are investigated by using PSPICE simulation. The results obtained are compared with a general CMOS and a couple of previous BiCMOS tristate buffer circuits which are conventional BiCMOS and complementary BiCMOS tristate buffer circuits. It is shown that the proposed BiCMOS tristate buffer circuit outperforms other previous tristate buffer circuits. At lower supply voltage, the proposed circuit has been shown more advantageous speed over previous circuits and it guarantees speed advantage over previous circuits even supply voltage application is at 1.5 volt. The pass transistor technique with a single MOS transistor driving is used to improve the driving capability. Furthermore, a complementary BiCMOS charge pump technique is used to eliminate the voltage loss due to base-emitter turn on voltage and to enhance the driving capability. With the positive and negative charge pump, it can be realized a high speed at low voltage with full swing operation without performance degradation due to shunt CMOS circuit as same as previous complementary BiCMOS tristate buffer circuit.

In this study, an improved heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) active mixer is designed and fabricated. The HBT MMIC active mixer that is integrated with a low-noise amplifier (LNA) and active power adder can not only achieve high isolation, but can also dispense with one active component and reduce power consumption at the same time. Measurement results show that the conversion gain, LO-RF isolation, and double sideband noise figure (DSB-NF) of the proposed mixer are 22 dB, 40 dB, and 7 dB, respectively.

A high-speed bipolar ECL comparator circuit with a latch is described. The spike noise generated by charging the base-to-emitter diffusion capacitor on the transition of differential transistors' switching in a sample-and-latch circuit is reduced by inserting the emitter degeneration resistors so that neither of them becomes completely cut off. The frequency bandwidth of a pre-amplifier is increased by using coupled inductors as differential loads. As a result, -3 dB frequency bandwidth of a pre-amplifier becomes 10 GHz, and 4 GS/s operation with 6-bit equivalent precision from a 3.3 V power supply is confirmed by the circuit simulation using device parameters from the 25 GHz silicon bipolar process.

A Switched-Opamp is a device in SC circuits for replacing switches with Opamps which operate like a switch. This technique can be acheived in very low voltage operation. In this paper, we present a design for a Switched-Opamp that can operate at a low supply voltage during the ON-phase and can maintain a high output impedance during the OFF-phase.

This paper analyzes the input-dependent sample-time error in MOS sampling circuits caused by the finite slope of the sampling clock, and clarifies the following: (i) Input-dependent sampling jitter causes phase modulation in the sampled data. (ii) The formulas for SDR due to such sampling errors are explicitly derived. (iii) NMOS sampling circuits generate even-order harmonics, which are greatly reduced by using a differential topology. (iv) CMOS sampling circuits without clock skew between Vclk and generate odd-order harmonics which a differential topology cannot help cancel, whereas circuits with clock skew generate even-order as well as odd-order harmonics. (v) For single-ended sampling circuits, the SDR of CMOS circuits without clock skew is better than that of NMOS circuits. (vi) NMOS differential sampling circuits are relatively insensitive to input-dependent sampling-time error effects, which would be the best regarding to the input-dependent sampling-time error effects. (vii) Its effects in case of NMOS differential samplers with finite skew between plus and minus path clocks are discussed. (viii) Its effects in CMOS samplers with finite skew between PMOS and NMOS clocks are discussed.

This paper presents a novel class of sigma-delta modulator topologies for low-voltage, high-speed, and high-resolution applications with low oversampling ratios (OSRs). The main specifications of these architectures are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal to noise ratio (SNR) with a low OSR, and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections. To demonstrate the efficiency of the proposed modulator architectures a prototype with HSPICE is implemented. A low-power two-stage class A/AB OTA with modified common mode feedback (CMFB) circuit in the first stage is used to implement the fourth order modulator. Simulation results with OSR of 16 give signal to noise plus distortion ratio (SNDR) and dynamic range (DR) of 90-dB and 92.5-dB including the circuit noise in the 1.25-MHz signal bandwidth, respectively. The circuit is implemented in a 0.13-µm standard CMOS technology. It dissipates about 40-mW from a single 1.2-V power supply voltage.