This CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with only 6.25 mm2 die area for IEEE 802.11b standard. The transceiver is implemented in 0.25 µm CMOS process with 2.7 V supply voltage, and achieves a -86 dBm 11 Mb/s receive sensitivity and a 2 dBm transmit output power.

This paper describes the characteristics of lithium-ion cells developed for stationary use, as in the case of stand-by sources in power systems. The effect of a cell-voltage-equalizing circuit developed for batteries of cells is also demonstrated. The tested lithium-ion cells were suitable to be charged by the constant-current, constant-voltage (CCCV) method and could be charged efficiently over a wide range of temperatures. They also showed good discharge performance with little dependence on the discharge current and temperature. Total capacity reduction of over 60% can be expected in batteries of lithium-ion cells. The cell-voltage-equalizing circuit was shown to be useful and necessary for batteries of lithium-ion cells in order to suppress deviations in the cell voltage and capacity loss.

An ultra-small (0.3-mm0.3-mm0.06-mm) radio frequency identification chip called the µ-chip has been developed for use in a wide range of individual recognition applications. The chip is designed to be thin enough to be applied to paper and paper-like media that are widely used in retailing to create certificates with monetary value, as well as to token-type devices. The µ-chip has been designed and fabricated using 0.18-µm standard CMOS technology. This ultra-small RFID chip also has a low-cost oriented device structure of a double-surface electrode to simplify the process of connecting the antenna and chip. The measured characteristics of the prototype chip are presented, demonstrating the capability of the new chip as an RFID device.

A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 µm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.

A novel millimeter wave quadruple-push oscillator is presented in this paper. The quadruple-push oscillator consists of four identical sub-circuits and a ring resonator that is used as a common resonator. It is well known that there are two orthogonal resonant modes on a one-wavelength ring resonator. According to this resonant characteristic, two orthogonal push-push oscillations can be set up in the quadruple-push oscillator, and there is a phase difference of 90among four sub-circuits due to nonlinear performance. Therefore, the four identical sub-circuits can oscillate at the same fundamental frequency f0, and the fundamental oscillating signal of one sub-circuit has phase differences of 90, 180and 270to that of the others, and the desired fourth harmonic signals can be combined due to their in phase relations, and the undesired fundamental signals, the second harmonic signals, the third harmonic signals and so on can be suppressed when the oscillating signals of the four sub-circuits are added in phase. The principle is firstly explained in this paper, and is proved in the experiment of a Ka-band quadruple-push oscillator. The measured output power of the desired fourth harmonic signal (4f0) was +1.67 dBm at the frequency of 35.8 GHz. The measured suppression of the undesired signals of the fundamental signal (f0), the second harmonic signal (2f0), the third harmonic signal (3f0) and the fifth harmonic signal (5f0) were -18.0 dBc, -17.9 dBc, -17.8 dBc and -35.5 dBc, respectively. The measured phase noise performances at 35.8 GHz were -104.0 dBc/Hz and -82.3 dBc/Hz at the offset frequency of 1 MHz and 100 kHz, respectively.

This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical structure when verifying timed circuits. Experimenting with the STARI and DME circuits, the proposed approach shows its effectiveness.

For a highly nonlinear circuit design such as an active frequency multiplier, performing an input impedance "match" is not a straightforward problem. In this work, an analysis of nonlinear input impedance matching in active microwave frequency multipliers is presented. By utilizing harmonic balance simulation of an idealized device model, fundamental aspects of performing an input "match" are explored for classical frequency doubler and frequency tripler configurations. The analysis is then repeated using a realistic device model, verifying the efficacy of using nonlinear input impedance matching to improve the output power and return loss characteristics of a multiplier.

A technique to control the radiation pattern of an NRD-guide-compatible pyramidal horn antenna, which consists of a tapered dielectric rod inserted into the horn, was developed for multiple access LAN applications at 60 GHz. By using this simple technique, the half-power beamwidth can be controlled from 11to 40.

Finding DC operating points of transistor circuits is a very important and difficult task. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For efficiency of homotopy methods, it is important to construct an appropriate homotopy function. In conventional homotopy methods, linear auxiliary functions have been commonly used. In this paper, a homotopy method for solving transistor circuits using a nonlinear auxiliary function is proposed. The proposed method utilizes the nonlinear function closely related to circuit equations to be solved, so that it efficiently finds DC operating points of practical transistor circuits. Numerical examples show that the proposed method is several times more efficient than conventional three homotopy methods.

We present a low-phase-noise and frequency-tunable photonic millimeter-wave (MMW) generator based on two-mode beating. The generator consists of a single-mode laser, an external optical intensity modulator, and a planar lightwave circuit (PLC) on which an arrayed-waveguide grating (AWG) and 3-dB optical combiners are integrated. Because the AWG and the optical combiners are connected with optical waveguides and the optical path length difference between the two modes filtered by the AWG is kept constant, the phase fluctuation of the generated MMW signal is suppressed. The generator can generate MMWs with a phase noise of less than -75 dBc/Hz at 100 Hz and has a frequency tunability in a range of 90 to 125 GHz. The generator can be applied for the local oscillator (LO) in 10-Gbit/s wireless links that use heterodyne detection.

In order to reduce the size of a wireless system, we propose a design theory for the broadband impedance matching circuit which connects an electrically small antenna (ESA) to a semiconductor amplifier. We confirmed its validity for the case of connection between a small slot loop antenna with a small radiation resistance of Ra =0.776 Ω and a semiconductor amplifier with high input impedance of ZL =321-j871 Ω with the aid of the simulations by the electrical circuits using transmission lines as well as the electromagnetic field (EM field) simulator. We also made experiments on this antenna with matching circuits using high temperature superconductor YBCO thin films on MgO substrates.

This paper describes a system architecture along with signal processing technique which allows a reduction in the complexity of a 3.1-10.6 GHz Ultra-Wideband radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end down-converts the signal frequency by subsampling, thus, requiring substantially less hardware than a traditional narrowband approach. However, the simplified receiver front end shows a high sensitivity to timing offset. By proposing an analytic signal processing technique, the vulnerability of timing offset is mitigated; furthermore, a time resolution finer than the sampling period is achieved, which is useful for locationing or ranging applications. Analysis and simulations of system specifications are also provided in this paper.

This paper presents the analysis of hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensation methods, which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non-dominant poles and zeros of the hybrid cascode compensation are about 40 percent greater than those of the conventional cascode compensation. Circuit level simulation results are provided to show the accuracy of the calculated expressions and also the usefulness of the proposed cascode compensation technique.

A feedforward-based active shielding technique for digital noise suppression is more preferred for its capability of reducing the noise on the entire area inside the guard ring. In order to compensate for the variation of substrate parameters, an automatic control scheme to tune the gain of the active shield circuit is proposed. Simulation results show the effectiveness of the proposed system in reducing the digital noise regardless of circuit layout. Simulation results also show that noise suppression improvement from passive guard ring to active shield with tuning is 20 dB or one tenth while that from active shield without tuning to active shield with tuning is 12 dB.

Recently, efficient algorithms have been proposed for finding all characteristic curves of one-port piecewise-linear resistive circuits. Using these algorithms, a middle scale one-port circuit can be represented by a piecewise-linear resistor that is neither voltage nor current controlled. In this letter, an efficient algorithm is proposed for finding all dc operating points of piecewise-linear circuits containing such neither voltage nor current controlled resistors.

Direct parameter extraction is believed to be the most accurate method for equivalent-circuits modeling of heterojunction bipolar transistors (HBT's). Using this method, the parasitic elements, followed by the intrinsic elements, are determined analytically. Therefore, the quality of the extrinsic elements extraction plays an important role in the accuracy and robustness of the entire extraction algorithm. This study proposes a novel extraction method for the extrinsic elements, which have been proven to be strongly correlated with the intrinsic elements. By utilizing the specific correlation, the equivalent circuit modeling is reduced to an optimization problem of determining six specific extrinsic elements. Converting the intrinsic equivalent circuit into its common-collector configuration, all intrinsic circuit elements are extracted using exact closed-form equations for both the hybrid-π and the T-topology equivalent circuits. Additionally, a general explicit equation on the total extrinsic elements is derived, subsequently reducing the number of optimization variables. The modeling results are presented, showing that the proposed method can yield a good fit between the measured and calculated S parameters.

In this letter, two kinds of MOS operational transconductance amplifiers (OTAs) based on combiners are presented. Each OTA has the following advantages; one of the proposed OTAs (OTA-1) can be operated at low supply voltage and the other OTA (OTA-2) has wide bandwidth. Through HSPICE simulations with a standard 0.35 µm CMOS device parameters, the operation under the supply voltage of 1.5 V for OTA-1 and the -3 dB bandwidth of several gigahertz for OTA-2 are confirmed.

A structure of a track-and-hold (T/H) circuit based on a pair of complementary floating-gate (FG) MOS transistors is introduced. Its main features include low complexity, low operating supply voltage and gain insensitivity to device mismatches, leading to efficient realization of numerous baseband functions in modern communication systems. The detailed operation and performance analysis of the FG T/H circuit are given. Functional verification of the circuit is provided through a breadboard experiment. The effectiveness of the circuit is verified via simulations where the single T/H cell operating at 10 MHz clock frequency exhibits gain variation less than 0.13% and a dynamic range over 71 dB with the coupling capacitance of 300 fF at 1.5 V supply and 12.75 µW power consumption. As a demonstration on its practical viability, the designed FG T/H cell was also utilized to realize a 10 MS/s 7-tap analog correlator for possible use in modern communication applications.

In a switched-capacitor (SC) circuit, the major block is an operational transconductance amplifier (OTA) designed in order to form a feedback loop. However, the OTA is the block that consumes most of the power in SC circuits. This paper proposes the use of a class-C inverter instead of the OTA in SC circuits and a corresponding switches configuration for extremely low power applications. A detailed analysis and design trade-offs are also provided. Simulation and experimental results show that sufficient performance can be obtained even though a class-C inverter is used. The second-order biquad filter and the second-order SC sigma-delta (ΣΔ) modulator based on a class-C inverter are designed. These circuits have been fabricated with a 0.35-µm CMOS process. The measurement results of the fabricated SC biquad filter show a 59-dB signal-to-noise-plus-distortion ratio (SNDR) for a 0.2-Vp-p input signal and 0.9-V dynamic ranges. The power consumption of the biquad filter is only 0.4 µW with a 1-V power supply. The measurement results of the fabricated ΣΔ modulator show a 61-dB peak SNR for a 1.6-kHz bandwidth with a sample rate of 200 kHz. The modulator consumes 0.8 µW with a 1-V power supply.

In this paper, we present the classification of small antennas based on statistical data. The three categories of downsizing methods are loading a matching circuit, changing the current path, and using dielectric/magnetic materials. These categories are explained using several examples. In this paper, we show that the miminum Q value as a fundamental limit defined by an infinitesimal dipole is effective for determining the index factor of small antennas. Radiation efficiency measurements for small antennas are also discussed.