High-frequency characteristics of SiGe heterojunction bipolar transistors with different emitter sizes are studied based on pulsed measurements. Because the self-heating effect in transistors will enhance the Kirk effect, as the devices operate in high current region, the measured cutoff frequency and maximum oscillation frequency decrease with measurement time in the pulsed duration. By analyzing the equivalent small-signal device parameters, we know the reduction of cutoff frequency and maximum oscillation frequency is attributed to the reduction of transconductance and the increase of junction capacitances for fixed base-emitter voltage, while it is only attributed to the degradation of transconductance for fixed collector current. Besides, the degradation of high-frequency performance due to self-heating effect would be improved with the layout design combining narrow emitter finger and parallel-interconnected subcells structure.

Direct parameter extraction is believed to be the most accurate method for equivalent-circuits modeling of heterojunction bipolar transistors (HBT's). Using this method, the parasitic elements, followed by the intrinsic elements, are determined analytically. Therefore, the quality of the extrinsic elements extraction plays an important role in the accuracy and robustness of the entire extraction algorithm. This study proposes a novel extraction method for the extrinsic elements, which have been proven to be strongly correlated with the intrinsic elements. By utilizing the specific correlation, the equivalent circuit modeling is reduced to an optimization problem of determining six specific extrinsic elements. Converting the intrinsic equivalent circuit into its common-collector configuration, all intrinsic circuit elements are extracted using exact closed-form equations for both the hybrid-π and the T-topology equivalent circuits. Additionally, a general explicit equation on the total extrinsic elements is derived, subsequently reducing the number of optimization variables. The modeling results are presented, showing that the proposed method can yield a good fit between the measured and calculated S parameters.

In this paper, an accurate and low-cost method for on-wafer noise figure measurement, specifically designed for low-noise amplifiers (LNAs), will be proposed. An experiment conducted on a 5 GHz LNA demonstrates that a good agreement can be reached between the measurement result of the proposed method and that of a commercial noise parameter measurement system.

RF MOSFET's are usually measured in common source configuration by a 2-port network analyzer, and the common gate and common drain S-parameters cannot be directly measured from a conventional 2-port test structure. In this work, a 4-port test structure for on-wafer measurement of RF MOSFET's is proposed. Four-port measurements for RF MOSFET's in different dimensions and the de-embedded procedures are performed up to 20 GHz. The S-parameters of the RF MOSFET in common source (CS), common gate (CG), and common drain (CD) configurations are obtained from a single DUT and one measurement procedure. The dependence of common source S-parameters of the device on substrate bias are also shown.

In this study, a cascade open-short-thru (COST) de-embedding procedure is proposed for the first time for on-wafer device characterization in the RF/microwave frequency regime. This technique utilizes the "open" and "short" dummy structures to de-embed the probe-pad parasitics of a device-under-test (DUT). Furthermore, to accurately estimate the input/output interconnect parasitics, including the resistive, inductive, capacitive, and conductive components, the "thru" dummy device has been characterized after probe-pad de-embedding. With the combination of transmission-line theory and cascade-configuration concept, this method can efficiently generate the scalable and repeatable interconnect parameters to completely eliminate the redundant parasitics of the active/passive DUTs of various device sizes and interconnect dimensions. Consequently, this method is very suitable for the on-wafer automatic measurement.

In this letter, a new computation method for the noise parameters of a linear noisy two-port network is introduced. A new error function, which considers noise figure and source admittance error simultaneously, is proposed to estimate the four noise parameters. The global optimization of the error function is searched directly by using a genetic algorithm.

In this work, a simple method for extracting MOSFET threshold voltage, effective channel length and channel mobility by using S-parameter measurement is presented. In the new method, the dependence between the channel conductivity and applied gate voltage of the MOSFET device is cleverly utilized to extract the threshold voltage, while biasing the drain node of the device at zero voltage during measurement. Moreover, the effective channel length and channel mobility can also be obtained with the same measurement. Furthermore, all the physical parameters can be extracted directly on the modeling devices without relying on specifically designed test devices. Most important of all, only one S-parameter measurement is required for each device under test (DUT), making the proposed extraction method promising for automatic measurement applications.