Tuan-Anh PHAN Chang-Wan KIM Yun-A SHIM Sang-Gug LEE
This paper presents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18 µm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528 MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.
Jing LI Juebang YU Hiroshi MIYASHITA
Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.
Dong Yong SHIN Yojiro MATSUEDA Ho Kyoon CHUNG
We have developed new current demultiplexer TFT circuits for AMOLED and applied the circuits to 2.2-in. QVGA AMOLED. The combination of the current demultiplexer and our voltage boosted current programmed pixel can achieve good uniformity of display image and a compact module.
Tomoya KITAI Tomohiro YONEDA Chris MYERS
This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure are obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits.
Ming-Dou KER Jung-Sheng CHEN Ching-Yun CHU
A new sub-1-V CMOS bandgap voltage reference without using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-µm CMOS process, where the occupied silicon area is only 177 µm106 µm. The experimental results have shown that, with the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/ from -10 to 120 without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10 kHz.
Yu IMAI Kiyotaka YAMAMURA Yasuaki INOUE
Finding DC operating points of nonlinear circuits is an important problem in circuit simulation. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. There are several types of homotopy methods, one of which succeeded in solving bipolar analog circuits with more than 20000 elements with the theoretical guarantee of global convergence. In this paper, we propose an improved version of the homotopy method that can find DC operating points of practical nonlinear circuits smoothly and efficiently. Numerical examples show the effectiveness of the proposed method.
Futoshi KUROKI Kazuya MIYAMOTO Shigeo NISHIDA
A higher mode tri-plate strip transmission line, in which the first higher mode propagates, was developed to realize mass production of millimeter-wave integrated circuits for application in intelligent transport systems, and its transmission characteristics were investigated. The design diagram of this guided mode was determined and a higher mode tri-plate strip transmission line was fabricated at 30 GHz. The dispersion curve was found to be similar to that of a rectangular waveguide and a low transmission loss of less than 10 dB/m was obtained. For construction of some functional devices, two types of basic reactance components, such as a gap and a slot, were expressed by equivalent circuits. The former was expressed by capacitive parameters, and the latter was expressed by an ideal transformer with inductive parameters. The gap-coupled circuit was successfully employed for a 3-pole 0.1 dB Chebyshev ripple band-pass filter with a small excess insertion loss of less than 1 dB at a center frequency of 32 GHz, as well as no spurious response in a bandwidth from 26.5 GHz to 40 GHz. The slot element acted as a matching circuit and a suppressor of the lowest mode, which is the TEM mode in the tri-plate strip transmission line. Moreover, this element was applied to a mode transformer between the lowest mode and the first higher mode.
Koichi TANNO Kiminobu SATO Hisashi TANAKA Okihiko ISHIZUKA
In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.
Tsukasa IDA Shinsaku SHIMIZU Toshimasa MATSUOKA Kenji TANIGUCHI
Wired CDMA interface with adaptivity for interconnect capacitances is designed to receive transmitted data even under a wide variety of connection topologies. The variable gain amplifier (VGA) is one of key circuit blocks to realize the adaptivity for interconnect capacitances. The system level numerical simulations derive the VGA specifications that the required VGA gain range is from 0.37 to 2.0, which can be realized easily using a multiple-differential-pair technique.
Futoshi KUROKI Makoto KIMURA Tsukasa YONEYAMA
A transition between an NRD guide, suitable for construction of high performance millimeter-wave integrated circuits, and a microstrip line, being used to mount semiconductor devices such as HEMT, HBT, and MMIC, was developed at 60 GHz. The main emphasis was placed on the manner of field matching between the NRD guide and the microstrip line. We propose adoption of this a new transition structure employing a vertical strip line, which can be easily coupled to the NRD guide, and a coaxial line connected to the microstrip line. Moreover, we applied a packaging structure with a choke circuit for the microstrip line to prevent undesired leakage between the NRD guide and the microstrip line. The insertion loss of the fabricated transition was measured to be less than 0.5 dB in the bandwidth of 3 GHz at a center frequency of 60.5 GHz. The transition was applied to MMIC amplifier integration in the NRD guide at 60 GHz. The forward and reverse gains were measured to be 15 dB and -20 dB, respectively, at 60 GHz.
The most obvious architectural solution for high-speed fuzzy inference is to exploit temporal parallelism and spatial parallelism inherited in a fuzzy inference execution. However, in fact, the active rules in each fuzzy inference execution are often only a small part of the total rules. In this paper, we present a new architecture that uses less hardware resources by discarding non-active rules in the earlier pipeline stage. Compared with previous work, implementation data show that the proposed architecture achieves very good results in terms of the inference speed and the chip area.
Koichi KOIBUCHI Koichiro SAWA Takashi HONMA Takumi HAYASHI Kuniyoshi UEDA Hiroshi SASAKI
An eddy-current type proximity sensor is a non-contact type sensing device to detect the approach of a conductor by increase of equivalent AC resistance of excitation coil due to eddy current loss in the conductor. In this paper, electromagnetic characteristics of the actual proximity sensor are calculated by FEM and the validity of numerical analysis results are studied. Furthermore, two models that has modified magnetic circuit geometry based on the actual sensor are designed and calculated as numerical experiments. Calculated results are shown as enhanced sensing index or electromagnetic characteristics of the modified sensor. In conclusions, knowledge about the magnetic circuit geometry of the sensor is applied for the enhancement of sensing property.
This paper presents the design of new fully differential CMOS class A and class AB current-mode transmitters for multi-Gbps serial links. A high multiplexing speed is achieved by multiplexing at low-impedance nodes and inductive shunt peaking with active inductors. The fully complementary operation of the multiplexers and the fully differential configuration of the transmitters minimizes the effect of common-mode disturbances and that of EMI from channels to neighboring devices. Large output current swing is obtained by making use of differential current amplifiers and the differential rail-to-rail configuration. The constant current drawn from the supply voltage minimizes the noise injected into the substrate. The transmitters have been implemented in TSMC's 1.8 V 0.18 µm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V device models. Simulation results confirm that the proposed transmitters are capable of transmitting data at 10 Gbps.
Sang Wook PARK Jae Cheol JU Dong Chul PARK
In this paper, crosstalk between multiconductor transmission lines of finite length in arbitrary directions on a printed circuit board is studied by using a circuit-concept approach. The circuit-concept approach of (2+1) finite-length lines is expanded for the crosstalk calculation of (n+1) lines where n>2.2n-port network expression is derived from the modified telegrapher equations. The effect of via currents flowing through the vertical short line sections at the line terminals is also investigated. Due to this expansion the derived equations for (n+1) lines are expected to be easily applied for crosstalk analysis of a variety of complex structures such as via fences and guard traces, etc.
Toshio MATSUSHIMA Shinya TAKAGI Seiichi MUROYAMA Toshio HORIE
This paper describes the characteristics of lithium-ion cells developed for stationary use, as in the case of stand-by sources in power systems. The effect of a cell-voltage-equalizing circuit developed for batteries of cells is also demonstrated. The tested lithium-ion cells were suitable to be charged by the constant-current, constant-voltage (CCCV) method and could be charged efficiently over a wide range of temperatures. They also showed good discharge performance with little dependence on the discharge current and temperature. Total capacity reduction of over 60% can be expected in batteries of lithium-ion cells. The cell-voltage-equalizing circuit was shown to be useful and necessary for batteries of lithium-ion cells in order to suppress deviations in the cell voltage and capacity loss.
Yoshitsugu KAMIMURA Katsuo KOMORI Masahiro SHOJI Yoshifumi YAMADA Soichi WATANABE Yukio YAMANAKA
The radio-frequency protection guideline of Japan recommend the limits of contact current for contact hazard due to an ungrounded metallic object under an electromagnetic field in the frequency range from 10 kHz to 15 MHz. To arrange the standard measurement methods of contact current in Japan, the contact body impedance for the Japanese in the frequency range from 75 kHz to 15 MHz is obtained, and the simplified equivalent circuit is determined using nonlinear least squares method. In addition, the human body impedance is obtained from numerical simulation using the impedance method and voxel human model, and compared it with measured one.
Yongpeng MENG Shenli JIA Mingzhe RONG
Using the Vibration signatures obtained during the operations as the original data, a mechanical condition monitoring method for vacuum circuit breaker is developed in this paper. The method combined the time-frequency analysis and the condition recognition based on artificial neural network. During preprocessing, the vibration signature was decomposed into individual frequency bands using the arithmetic of wavelet packets. The signal energy in the main frequency bands was used to form the condition feature vector, which was input to the artificial neural network for condition recognition. By introducing the parameter of approximation degree, a new recognition arithmetic based on Radial Basis Function was constructed. This approach could not only distinguish these conditions that belong to different known condition modes but also distinguish new condition modes.
Yong-Hsiang HSIEH Wei-Yi HU Wen-Kai LI Shin-Ming LIN Chao-Liang CHEN David J. CHEN Sao-Jie CHEN
This CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with only 6.25 mm2 die area for IEEE 802.11b standard. The transceiver is implemented in 0.25 µm CMOS process with 2.7 V supply voltage, and achieves a -86 dBm 11 Mb/s receive sensitivity and a 2 dBm transmit output power.
Tae-Hyoung KIM Kwang-Jin LEE Uk-Rae CHO Hyun-Geun BYUN
This paper describes a digital impedance controller (DIC) [1] for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23 Ω to 140 Ω with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is 2.26% with RQ ranging from 23 Ω to 53 Ω, the same range covered by conventional scheme. The high resolution and wide range impedance control is implemented by using automatic gate voltage optimization. The amount of jitter caused by quantization error is 6.9 ps while 13.8 ps in conventional scheme. The data input valid window is 623 ps at 0.75200 mV and maximum eye open is 641 mV meaning about 10% improvement at 1.5 Gbps/pin DDR3 SRAM interface.
Mingzhe RONG Yi WU Qian YANG Guangxia HU Shengli JIA Jianhua WANG
This paper is devoted to simulate the arc movement in the quenching chamber of the low-voltage circuit breaker. Based on a group of governing equations, a three-dimensional (3-D) arc model is built and solved by a modified commercial code. According to the simulated results, some phenomena such as a 'bulge' in front of the arc column, a tail in the rear of the arc column, arc shrinkage near the electrodes and arc movement characteristics versus different chamber configuration and external magnetic field are found, and the mechanism of the above phenomena is described in detail. Finally, in order to verify the simulation results, arc movement is investigated by hi-spec motion analyzer experimentally.