IEICE TRANSACTIONS on Fundamentals
Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit
Summary :
In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.10 pp.2696-2698
- Publication Date
- 2005/10/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.10.2696
- Type of Manuscript
- Special Section LETTER (Special Section on Nonlinear Theory and its Applications)
- Category
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Koichi TANNO, Kiminobu SATO, Hisashi TANAKA, Okihiko ISHIZUKA, "Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 10, pp. 2696-2698, October 2005, doi: 10.1093/ietfec/e88-a.10.2696.
Abstract: In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.10.2696/_p
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@ARTICLE{e88-a_10_2696,
author={Koichi TANNO, Kiminobu SATO, Hisashi TANAKA, Okihiko ISHIZUKA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit},
year={2005},
volume={E88-A},
number={10},
pages={2696-2698},
abstract={In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.},
keywords={},
doi={10.1093/ietfec/e88-a.10.2696},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2696
EP - 2698
AU - Koichi TANNO
AU - Kiminobu SATO
AU - Hisashi TANAKA
AU - Okihiko ISHIZUKA
PY - 2005
DO - 10.1093/ietfec/e88-a.10.2696
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2005
AB - In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.
ER -
English
