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In this paper, a new compensation scheme and a corresponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5 V/150 mA LDO has been implemented using a 0.5-µm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33 µF and no ESR.
Koichi TANNO Kiminobu SATO Hisashi TANAKA Okihiko ISHIZUKA
In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of VDD + vin, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.
Koichi TANNO Kenya KONDO Okihiko ISHIZUKA Takako TOYAMA
In this letter, two kinds of MOS operational transconductance amplifiers (OTAs) based on combiners are presented. Each OTA has the following advantages; one of the proposed OTAs (OTA-1) can be operated at low supply voltage and the other OTA (OTA-2) has wide bandwidth. Through HSPICE simulations with a standard 0.35 µm CMOS device parameters, the operation under the supply voltage of 1.5 V for OTA-1 and the -3 dB bandwidth of several gigahertz for OTA-2 are confirmed.
Takashi MORIE Kenichi MURAKOSHI Makoto NAGATA Atsushi IWATA
This paper presents circuit techniques using pulse-width and pulse-phase modulation (PWM/PPM) approaches for VLSI implementation of nonlinear dynamical systems. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain, and also approximately implement continuous-time dynamics. Arbitrary nonlinear transformation functions are generated by the process in which a PPM signal samples a voltage or current source whose waveform in the time domain has the same shape as the desired transformation function. Because a shared arbitrary nonlinear voltage or current waveform generator can be constructed by digital circuits and D/A converters, high flexibility and real-time controllability are achieved. By using one of these new techniques, we have designed and fabricated a CMOS chaos circuit with arbitrary 1-D maps using a 0.6 µm CMOS process, and demonstrate from the experimental results that the new chaos circuit successfully generated various chaos with 7.5-7.8 bit precision by using logistic, tent and chaotic-neuron maps.