It is known that a high permittivity NRD guide suffers from irregular transmission phenomena. In this study, we clarified that this problem is caused by a mode coupling phenomenon between the operating and parasitic modes due to a small remaining asymmetrically air gap between the metal plates and high permittivity dielectric materials.

This paper presents a design procedure of a directional coupler consisting of a twofold symmetric four-port circuit with four identical matching networks at each port. The intrinsic power-split ratio and the equivalent admittance of the directional coupler are formularized in terms of the eigenadmittances of the original four-port without the matching networks. These formulas are useful for judgment on the realizability of a directional coupler in a given circuit structure and for design of the matching networks. Actually, the present procedure is applied to designing various quadrature hybrids and directional couplers, and its practical usefulness as well as several new circuit structures are demonstrated.

A mode transformer between the NRD guide and the vertical strip line was developed and applied to the right angle corner, T-junction, and 3-port junction at 60 GHz. Emphasis was placed on a fully CAD-based design procedure by using an electromagnetic field simulator. Agreement between the simulated and measured performances of the junction circuit was obtained, and thus the validity of the design procedure was confirmed. A well-balanced transmission coefficient of the 3-port junction, found to be 4 0.5 dB, was observed in the bandwidth of 2 GHz around a center frequency of 60 GHz.

A flexible transmission line, consisting of a thin ceramic-compounding Teflon strip, was devised by using a high permittivity LSE-NRD guide. This transmission line has the advantage of changeable shape. Low-loss performance was confirmed by measuring the transmission loss of the 180 degree bend and the S-shaped curve in the 60 GHz frequency band.

This paper presents a multiple-voltage high-level synthesis approach for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by maximization of task mobilities in that the increase of mobilities may raise the possibility of assigning tasks to low-voltage components. The mobility means the ability to schedule the starting time of a task. It is defined as the distance between its as-late-as-possible (ALAP) schedule time and its as-soon-as-possible (ASAP) schedule time. To earn task mobilities, we use loop shrinking, retiming and unfolding techniques. The loop shrinking can first reduce the iteration period bound (IPB) and, then, the others are employed for shortening the iteration period (IP) as much as possible. The minimization of IP results in high task mobilities. Finally, we can assign tasks with high mobilities to low-voltage components and, thus, minimize energy under resource and latency constraints. With considering the overhead of level conversion, our approach can achieve significant power reduction. In the case of the third-order IIR filter, the proposed approach can save up to 40.2% of power consumption.

Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.

A new analytical approach which reveals relationships between resonator parameters (unloaded Q-factor, coupling coefficient, and loaded Q-factor) and phase noise in microwave negative-resistance oscillators is presented. On the basis of Kurokawa's theory, this approach derives analytical expressions for the phase noise as a function of the resonator parameters (with particular emphasis on the coupling coefficient). Two types of negative-resistance oscillators--classified according to the manner in which the resonator is used in a circuit--are analyzed. These analyses use realistic circuit configurations and design procedures. The passive network connecting the active device and the resonator, which is shown to have important effects on the above-mentioned relationship, is taken into account. Validity of the new approach is verified through harmonic-balance simulations. The presented analytical approach can provide useful guidelines for choosing the resonator parameters, especially the value of the coupling coefficient, when designing microwave negative-resistance oscillators.

In this paper, a 20 GHz push-push oscillator using a ring resonator is proposed. The push-push oscillator adopts "dipole resonator push-push oscillator" circuit scheme, in which a common resonator plays two roles of frequency determining and power combining, and then the additional power combiner circuit required in conventional push-push oscillators can be eliminated. This kind of push-push oscillators has the advantages of the easy circuit design, the simple circuit configuation and the miniaturization of the circuit size. The output power is +4.5 dBm at the frequency of 20.34 GHz (2f0) with the phase noise of -98 dBc/Hz at the offset frequency of 1 MHz, and a high suppression of the undesired the fundamental frequency signal (f0) of -33 dBc is obtained.

In this paper a new method for the determination of the double layer capacitance and the internal inductance of a cell or battery is described. The resonance frequency of the double layer capacity with the internal inductance is determined by means of a phase measurement. The method can be used during operation of the battery. During a constant current discharge it is possible to predict the available discharge time from the resonance frequency at the start of the discharge and the actual resonance frequency. The method is tested with success on lead-acid batteries (VRLA, Plante) and nickel-cadmium batteries and it shows that the active surface is proportional to the state-of-charge (SOC). For primary zinc-MnO2 cells the measured electrical capacitance is not simply related to SOC.

This paper describes the effect of power line inductance and smoothing capacitance on a single-phase AC power supply system. Voltage fluctuations were calculated when the three main types of smoothing circuit (capacitor input, choke input, and power factor correction types) were used and the magnitude of power line inductance and smoothing capacitance were changed. First, we show the difference in voltage fluctuation in the case of constant resistance and negative resistance in a DC-DC converter. Second, we show the waveforms for which the power line inductance affects the voltage fluctuation of the AC power supply system. Finally, we propose the boundary condition for the power line inductance affecting the voltage fluctuation of the AC power supply system and estimate AC power supply system stability.

This paper presents CrtSmile--a CAD tool for the automatic extraction of layout-dependent substrate effects for RF MOSFET modeling. CrtSmile incorporates a new scalable substrate model, which depends not only on the geometric layout information of a transistor (the number of gate fingers, finger width, channel length and bulk contact location), but also on the transistor layout and bulk patterns. We show that this model is simple to extract and has good agreement with measured data for a 0.35 µm CMOS process. CrtSmile reads in the layout information of RF transistors in the CIF/GDSII format, performs a pattern-based layout extraction to recognize the transistor layout and bulk patterns. A scalable layout-dependent substrate model is automatically generated and attached to the standard BSIM3 device model as a sub-circuit for use in circuit simulation. A low noise amplifier is evaluated with the proposed CrtSmile tool, showing the importance of layout effects for RF transistor substrate modeling.

This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

In this paper, a new computing paradigm suitable for analog circuit systems is described in comparison to the digital circuit systems. The analog circuit systems have some disadvantages especially in terms of accuracy and stability, but there are some applications that don't require accuracy or stability in circuit component. The new computing concept for such applications, 'inaccurate' information processing, or 'rough' information processing, is proposed and described as well as some examples of such applications.

An experimental model of a redox microarray, which provides a foundation for constructing future massively parallel molecular computers, is proposed. The operation of a redox microarray is confirmed, using an experimental setup based on an array of microelectrodes with analog integrated circuits.

This paper presents circuit techniques using pulse-width and pulse-phase modulation (PWM/PPM) approaches for VLSI implementation of nonlinear dynamical systems. The proposed circuits implement discrete-time continuous-state dynamics by means of analog processing in a time domain, and also approximately implement continuous-time dynamics. Arbitrary nonlinear transformation functions are generated by the process in which a PPM signal samples a voltage or current source whose waveform in the time domain has the same shape as the desired transformation function. Because a shared arbitrary nonlinear voltage or current waveform generator can be constructed by digital circuits and D/A converters, high flexibility and real-time controllability are achieved. By using one of these new techniques, we have designed and fabricated a CMOS chaos circuit with arbitrary 1-D maps using a 0.6 µm CMOS process, and demonstrate from the experimental results that the new chaos circuit successfully generated various chaos with 7.5-7.8 bit precision by using logistic, tent and chaotic-neuron maps.

We present a built-in self-reconfiguring system for a mesh-connected processor array where faulty processor elements are compensated for by spare processing elements located in one row and one column. It has advantages in that the number of spare processing elements is small and additional control circuits and networks for changing interconnections of processing elements is so simple that hardware overhead for reconfiguration is also small. First, to indicate the motivation to the proposed reconfiguration scheme, we briefly describe other schemes with the same number of spares as that of the proposed scheme where faulty processing elements are replaced using straight shifts toward spares, and compare their reconfiguration probabilities to each other. Then, we show that a variant of the proposed scheme has the highest probability. Next, we present a built-in self-reconfiguring system for the scheme and formally prove that it works correctly. It can automatically replace faulty processors by spare processors on detecting faults of processors.

We have proposed and theoretically verified a 2R (reshaping and regeneration) limiter circuit using continuous wave (CW) holding beam for cross-gain modulation (XGM) wavelength converter, through simulation. The gain clamping effect of semiconductor optical amplifier (SOA), which is caused by CW holding beam injected into SOA, was used to obtain the accurate optical gain and phase conditions for SOA's in 2R limiter circuit. XGM wavelength converter with the proposed 2R limiter circuit provides higher extinction ratio (ER) as well as more enhanced operation speed than any other wavelength converter. Our numerical results show that after the wavelength-converted signal from XGM wavelength converter passed the 2R limiter circuit, it was re-inverted with the improved ER of 30 dB at 5 Gb/s. In case of high-speed operation, great enhancement to decrease power penalty of about 12 dB was shown at 10 Gb/s.

In this paper, a novel CMOS defuzzification circuit using dual-output current conveyors (DO-CCII) is introduced. The behaviour of the proposed circuit has been verified with PSPICE using the models for 1.2 µm MIETEC CMOS process. The proposed circuit offers high-speed operation and high accuracy because of using second generation current conveyors (CCII). The designed circuit is suitable for fuzzy logic controllers using center of gravity (COG) defuzzification method.

First we introduce the high-frequency equivalent circuit model of the Fine Pitched Ball Grid Array (FPBGA) bonding for frequencies up to 20 GHz. The lumped circuit model of the FPBGA bonding was extracted based on S-parameters measurement and subsequent fitting of the model parameters. The test packages, which contain probing pads, coplanar waveguides and FPBGA ball bonding, were fabricated and measured. The suggested π-model of the FPBGA bonding consists of self-inductor, self-capacitor, and self-resistor components. From the extracted model, a solder ball of 350 µm diameter and 800 µm ball pitch has less than 0.08 nH self-inductance, 0.40 pF self capacitance, and about 10 mΩ self-resistance. In addition, the mutual capacitance caused by the presence of the adjacent bonding balls is included in the model. The FPBGA solder ball bonding has less than 1.5 dB insertion loss up to 20 GHz, and it causes negligible delay time in digital signal transmission. The extracted circuit model of FPBGA bonding is useful in design and performance simulation of advanced packages, which use FPBGA bonding.

A Power on Reset signal generation circuit referencing threshold voltage without standby current consumption has been proposed. The POR signal is generated when supply voltage is larger than the sum of threshold voltages of N- and P-MOSFET.