Results obtained from a study on junction properties of n-CdS/p-InP heterodiodes which were prepared as solar cells by the close-spaced technique are described. The junction properties were examined by means of injection electroluminescence. It has been shown that these diodes have very low interface state density at least in deep levels even for an as-grown sample from the fact that only an electroluminescence due to the band-to-band transitions was observed at room temperature. At liquid nitrogen temperature, however, luminescence spectra originated from both band-to-band and free-to-bound transitions were observed. The energy difference between the two spectral peaks was found to be 67 meV, which corresponds to the activation energy of typical acceptors in InP. The internal electroluminescent quantum efficiency was 12.8% at 77 K.

Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.

This paper describes a novel engineering change order (ECO) design method for large-scale, high performance LSIs, based on a patchwork-like partitioning technique. In conventional design methods, even when only small changes are made to the design after the placement and routing process, a whole re-layout must be done, and this is very time consuming. Using the proposed method, we can partition the design into several parts after logic synthesis. When design changes occur in HDL, only the parts related to the changes need to be redesigned. The netlist for the changed design remains almost the same as the original, except for the small changed parts. For partitioning, we used multiple-fan-out-points as partition borders. An experimental evaluation of our method showed that when a small change was made in the RTL description, the revised circuit part had only about 87 gates on average. This greatly reduces the re-layout time required for implementing an ECO. In actual commercial designs in which several design changes are required, it takes only one day to redesign.