IEICE TRANSACTIONS on Fundamentals
An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs
Summary :
This paper describes a novel engineering change order (ECO) design method for large-scale, high performance LSIs, based on a patchwork-like partitioning technique. In conventional design methods, even when only small changes are made to the design after the placement and routing process, a whole re-layout must be done, and this is very time consuming. Using the proposed method, we can partition the design into several parts after logic synthesis. When design changes occur in HDL, only the parts related to the changes need to be redesigned. The netlist for the changed design remains almost the same as the original, except for the small changed parts. For partitioning, we used multiple-fan-out-points as partition borders. An experimental evaluation of our method showed that when a small change was made in the RTL description, the revised circuit part had only about 87 gates on average. This greatly reduces the re-layout time required for implementing an ECO. In actual commercial designs in which several design changes are required, it takes only one day to redesign.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3351-3357
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3351
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis
Authors
Keyword
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Yuichi NAKAMURA, Ko YOSHIKAWA, Takeshi YOSHIMURA, "An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3351-3357, December 2005, doi: 10.1093/ietfec/e88-a.12.3351.
Abstract: This paper describes a novel engineering change order (ECO) design method for large-scale, high performance LSIs, based on a patchwork-like partitioning technique. In conventional design methods, even when only small changes are made to the design after the placement and routing process, a whole re-layout must be done, and this is very time consuming. Using the proposed method, we can partition the design into several parts after logic synthesis. When design changes occur in HDL, only the parts related to the changes need to be redesigned. The netlist for the changed design remains almost the same as the original, except for the small changed parts. For partitioning, we used multiple-fan-out-points as partition borders. An experimental evaluation of our method showed that when a small change was made in the RTL description, the revised circuit part had only about 87 gates on average. This greatly reduces the re-layout time required for implementing an ECO. In actual commercial designs in which several design changes are required, it takes only one day to redesign.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3351/_p
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@ARTICLE{e88-a_12_3351,
author={Yuichi NAKAMURA, Ko YOSHIKAWA, Takeshi YOSHIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs},
year={2005},
volume={E88-A},
number={12},
pages={3351-3357},
abstract={This paper describes a novel engineering change order (ECO) design method for large-scale, high performance LSIs, based on a patchwork-like partitioning technique. In conventional design methods, even when only small changes are made to the design after the placement and routing process, a whole re-layout must be done, and this is very time consuming. Using the proposed method, we can partition the design into several parts after logic synthesis. When design changes occur in HDL, only the parts related to the changes need to be redesigned. The netlist for the changed design remains almost the same as the original, except for the small changed parts. For partitioning, we used multiple-fan-out-points as partition borders. An experimental evaluation of our method showed that when a small change was made in the RTL description, the revised circuit part had only about 87 gates on average. This greatly reduces the re-layout time required for implementing an ECO. In actual commercial designs in which several design changes are required, it takes only one day to redesign.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3351},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3351
EP - 3357
AU - Yuichi NAKAMURA
AU - Ko YOSHIKAWA
AU - Takeshi YOSHIMURA
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3351
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - This paper describes a novel engineering change order (ECO) design method for large-scale, high performance LSIs, based on a patchwork-like partitioning technique. In conventional design methods, even when only small changes are made to the design after the placement and routing process, a whole re-layout must be done, and this is very time consuming. Using the proposed method, we can partition the design into several parts after logic synthesis. When design changes occur in HDL, only the parts related to the changes need to be redesigned. The netlist for the changed design remains almost the same as the original, except for the small changed parts. For partitioning, we used multiple-fan-out-points as partition borders. An experimental evaluation of our method showed that when a small change was made in the RTL description, the revised circuit part had only about 87 gates on average. This greatly reduces the re-layout time required for implementing an ECO. In actual commercial designs in which several design changes are required, it takes only one day to redesign.
ER -
English
