Finding DC operating points of nonlinear circuits is an important and difficult task. The Newton-Raphson method adopted in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. For the global convergence of homotopy methods, it is a necessary condition that a given initial solution is the unique solution to the homotopy equation. According to the conventional criterion, such an initial solution, however, is restricted in some very narrow region. In this paper, considering the circuit interpretation of homotopy equations, we prove theorems on the uniqueness of an initial solution for globally convergent homotopy methods. These theorems give new criteria extending the region wherein any desired initial solution satisfies the uniqueness condition.

This paper investigates the use of chaotic pulsewidth modulation (CPWM) scheme for electronic ballasts to eliminate visible striations (appearance of black and white bands along the lamp tube) in fluorescent lamps. As striations can be eliminated by superimposing a small amount of dc current or low frequency ac current to the electrodes to produce composite current waveform through the lamp, the underlying principle of this work is based on the fact that the power spectral density of the lamp current will be rich of low-frequency harmonics at the output of inverters switching with CPWM. Most importantly, the lamp life will not be affected with chaotic switchings, because the lamp current crest factor is found to be similar to the one with standard pulsewidth modulation (PWM) and the lamp current does not have dc component. The effectiveness of eliminating striations is confirmed experimentally with a T8 36W prototype.

A nonlinear circuit described by the forced Duffing's equation is known to display a rich variety of dynamical behavior. Coupling two Duffing's circuits by a linear resistor, we conclude that combinatorial resonances occur on weak coupling condition. In a coupled system, although symmetrical properties are usually observed, breaking of symmetry can lead to much more complex nonlinear resonant phenomena. In this paper, we discuss asymmetry in four cases of perturbation on parameters. Many bifurcation diagrams are presented. Comparing with symmetrical cases, we analyze the combinatorial resonances in coupled Duffing's circuit completely.

Brain subsystems have a high degree of information processing ability using nonlinear dynamics and although various neuron models and artificial neural networks have been investigated, the information processing functions of biological neural networks have not yet been clarified. Recently, various research efforts have confirmed that dendrites perform an important role in brain information processing. In this paper, we discuss the nonlinear characteristics of a hardware active dendrite model, in order to clarify information encoding and transmission via action potentials. That is to say, we show that our proposed model can reproduce the nonlinear characteristics of a biologically active dendrite. First, the hardware active dendrite model we propose is described. We next discuss the response characteristics for pulse stimuli using the model. As a result, when input pulses are applied to an active line, which is the basic structure of the dendrite model, it is shown clearly that backpropagation characteristics are acquired and that the characteristics are qualitatively in agreement with the characteristics of biological dendrites. Furthermore, we verify that the ratio of input to output frequency at the cell body is influenced by the backpropagation characteristics with two branches, which is the simplest structure in the active dendrite model. Thus, with backpropagation characteristics, the possibility that the model can carry out clearly the information processing of biological neural networks, is suggested.

The concept of an Ω-matrix was introduced by Nishi in order to estimate the number of solutions of a resistive circuit containing active elements. He gave a finite characterization by means of four conditions which are all satisfied if and only if the matrix under investigation is an Ω-matrix. In this note we show that none of the four conditions can be omitted.

It is very difficult to simultaneously achieve power and cost reductions in address-driver circuits of a plasma-display panel (PDP) unit in which an energy-recovery scheme utilizing the resonance of a series-connected inductor and electrode parasitic capacitors is used. This is because an increase in parasitic capacitance and high-speed circuit operation become necessary as the display panel becomes larger in size and higher in resolution. In particular, low-power operation of address-driver ICs is key to avoiding the installation of heat sinks on the ICs. We propose herein new power-dispersion methods that can greatly reduce the power dissipation of address-driver ICs even when large parasitic capacitance is driven at high speed. The proposed methods enable a reduction in the power dissipation of address-driver ICs without deteriorating the operational speed by dispersing their powers into external resistors, and by supplying power to address-driver ICs in two voltage steps during both rising and falling time intervals when the address changes. Our results indicate that the power dissipation of address-driver ICs and the total cost of the address drive unit of a plasma-display panel can be reduced to 29% and 53%, respectively, compared with those of the ICs and the unit that are driven by the conventional address-driving method.

In this paper, a novel circuit structure of Push-Push oscillator using λg/2 microstrip resonator is proposed, in which a common resonator plays two functions of frequency determining and power combining. This type of Push-Push oscillator is named "Dipole Resonator Push-Push oscillator" here, where an additional power combiner circuit required in conventional Push-Push oscillators can be eliminated. The Push-Push oscillator adopting this design concept has the advantages of the easy circuit design, the simple circuit structure and the miniaturization of the circuit size. As a most simple example of this design concept, a K-band Push-Push oscillator using a λg/2 microstrip resonator is designed and achieved. The high output power of +8.4 dBm at the frequency of 21.68 GHz (2f0) is obtained with the phase noise of -100.5 dBc/Hz at the offset frequency of 1 MHz. Besides, a high suppression of the undesired fundamental frequency signal (f0) of -26 dBc is realized.

This paper newly proposes a hollow ferrite waveguide which consists of a microstrip line loaded on two ferrite slabs with adjacent air gap. Dispersion relation of magnetostatic surface wave in the waveguide is derived by the two dimensional analysis, and reciprocal behavior for parallel bias magnetic field and nonreciprocal behavior for antiparallel bias magnetic field are shown. Propagation characteristic of magnetostatic surface wave in the hollow ferrite waveguide are experimentally demonstrated under both parallel and antiparallel bias magnetic field directions. Strong nonreciprocal behavior in the hollow guide was found for case of antiparallel bias field configuration. These experimental results are mostly in agreement with the dispersion diagram. A nonreciprocal four port junction is demonstrated as an application of the hollow ferrite waveguide.

This paper introduces a design for testability (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. First, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated to the circuit. Our approach is mostly based on path delay fault model. However the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases substantially with the increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.

Utilizing a macromodel which calculates the floating gate potential by combining resistances and dependent voltage and current sources, DC transfer characteristics for multi-input neuron MOS inverters and for those in the neuron MOS full adder circuit are simulated both at room temperature and at 77 K. Based on the simulated results, low temperature circuit failures are discussed. Furthermore, circuit design parameter optimization both for low and room temperature operations is described.

A linear-in-dB VGA of the current-divider type is fabricated in 0.25 µm CMOS technology. Two gain compensation techniques are proposed in order to compensate the gain deviations due to a MOSFET which has a square-law characteristic or an exponential-law characteristic determined by its current density. Temperature compensation techniques are also proposed. Measure results obtained at 380 MHz are a gain range of 80 dB, a gain error of 3 dB, and an NF of 11 dB.

The interrupting characteristics of low voltage current limiting circuit breakers have directly relationship with the magnitude and distribution of magnetic field produced by contact system and splitter plates. In order to analyze the influence of configuration of contact system on current limiting characteristics, 3D magnetic field of arc chamber (including contact system, arc, splitter plates) is calculated. Furthermore, the electromagnetic repulsion force of movable contact is also calculated. The results can be used to improve configuration of arc quenching chamber. The cooperation between operating mechanism and electromagnetic repulsion force is also analyzed in this paper.

This paper describes a new special purpose Variable Gain Amplifier (VGA) using 0.5µm digital CMOS process. The new architecture allows the gain to be varied more than 20dB, and does not trade bandwidth for gain. Despite low power consumption (22mW) from a 3.3 Volt supply, the circuit has 310MHz -3dB bandwidth and shows low THD (-45dB) over its full frequency range. The new VGA architecture does not use any capacitor or resistor array for gain adjustment, thus it is very compact (0.14mm 0.26mm) and requires less power than conventional designs.

Piecewise linear (PWL) circuit modules operating on sigma-delta (ΣΔ) modulated signals and nonlinear signal processors built of these modules are proposed. The proposed module library includes absolute circuits, min/max selectors and negative resistances. Their output signal-to-noise ratio is higher than 50dB when their oversampling ratio is 28. A nonlinear filter and a stochastic resonator are presented as applications of the PWL modules to ΣΔ domain signal processing. The filter is structured with 37% of logic gates consumed by an equivalent filter with a 5-bit parallel signal form.

This paper describes the realization of a dynamically reconfigurable logic LSI based on a novel parallel computer architecture. The key point of the architecture is its dual-structured cell array which enables dynamic and autonomous reconfiguration of the logic circuits. The LSI was completed by successfully introducing two specific features: fully asynchronous logic circuits and a homogeneous structure, only LUTs are used.

A new analog correlator circuit is proposed for direct sequence code division multiple access (DS-CDMA) demodulator. The circuit consists of only 16 switches, 4 capacitors and 2 level shifters. Control sequence requires only three clock phases. Simulation with code length of 127 reveals that the proposed circuit has a good ability to cancel off the charge error and dissipates 3.4mW at 128MHz. The circuit had been designed using a 0.6µm CMOS process. The area of 256µm 245µm is estimated to be 9 times smaller compared to other reported equivalent analog correlators.

This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.

We have formed simple polarization-controller arrays by inserting liquid crystal (LC) in trenches cut across planar lightwave circuits (PLCs). We fabricated LC layers for use as polarization controllers on PLCs in two ways; in one, the ultra-thin layer of LC is held in a cell that is inserted into a trench on the PLC while in the other, the trench is directly filled with the LC. The ultra-thin LC cell can change the phase of 1.55-µm light from 0 to 3π while the LC filling can change the phase of light at the same wavelength from 0 to 12π below 5Vrms. Two former parallel-aligned ultra-thin LC cells, where the directions of alignment of the liquid crystals are rotated by 45 relative to each other, are capable of converting light with an arbitrary input polarization to TE or TM polarization. Ultra-thin cells of twisted nematic LC can switch the polarization between TE and TM modes with an extinction ratio of -15dB. The array we fabricated had a pitch of 1 mm and 5 elements, but an array with more than 100 elements and a pitch below 125µm will easily be possible by using finely patterned transparent electrodes. We have also applied our techniques to the fabrication of LC-based variable optical attenuators (VOA) on the PLC.

Although the subgraph isomorphism problem has various important applications, it is generally NP-complete and difficult to solve. Though a custom computing circuit can reduce the execution time substantially, it requires considerable hardware resources and is inapplicable to large problems. This paper examines the feasibility of data dependent designs, which are particularly suitable to a Field Programmable Gate Array (FPGA). The data dependent approach drastically reduces hardware requirements. For graphs of 32 vertices, the average logic scale of data dependent circuits is only 5% of the corresponding data independent circuit. The data dependent circuit is estimated to be maximally 460 times faster than the software. Even if the circuit generation time is included, a data dependent circuit is estimated to be 2.04 times faster than software for graphs of 32 vertices. The performance gain would increase for larger graphs.

A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.