IEICE TRANSACTIONS on Electronics
Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs
Summary :
This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.5 pp.842-849
- Publication Date
- 2003/05/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
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Hisako SATO, Mariko OHTSUKA, Kazuya MAKABE, Yuichi KONDO, Kazumasa YANAGISAWA, Peter M. LEE, "Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 5, pp. 842-849, May 2003, doi: .
Abstract: This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_5_842/_p
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@ARTICLE{e86-c_5_842,
author={Hisako SATO, Mariko OHTSUKA, Kazuya MAKABE, Yuichi KONDO, Kazumasa YANAGISAWA, Peter M. LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs},
year={2003},
volume={E86-C},
number={5},
pages={842-849},
abstract={This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Efficient Application of Hot-Carrier Reliability Simulation to Delay Library Screening for Reliability of Logic Designs
T2 - IEICE TRANSACTIONS on Electronics
SP - 842
EP - 849
AU - Hisako SATO
AU - Mariko OHTSUKA
AU - Kazuya MAKABE
AU - Yuichi KONDO
AU - Kazumasa YANAGISAWA
AU - Peter M. LEE
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2003
AB - This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.
ER -
English
