This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.

In MPU and ASIC design with 0.2 µm BiCMOS LSIs, it is well known that interconnect delay becomes one of the key data to ensure high operating frequency. To verify the whole path delay accurately, one needs to create huge delay and waveform libraries which reflect updated process and interconnect structure as well as device performance. Because of the necessity for more than 100 k times of circuit simulation to create the libraries, it was impossible to update the library quickly including process variation effects. In this paper, we have proposed a realistic new method to generate the libraries on the basis of RSM (Response Surface Method). In application for a BiCMOS ASIC process, we have verified that the new method has achieved the reduction of library creation time to 1/100 within the delay error of 3%. This technique can be used in our TCAD and DA framework, which gives a predictive TCAD generation of delay libraries in concurrent ASIC system and process development.