A new methodology for simulation-based CMOS process design has been proposed, using a Hierarchical Response Surface Method (HRSM) and an efficient experimental calibration. The design methodology has been verified using a 0.4 micron CMOS process. The proposed HRSM achieved a 60% reduction of process and device design cost in comparison with those of conventional TCAD. The procedure was performed in conjunction with an experimental calibration technique to provide a reliable threshold voltage prediction including process variation effects. The total CPU cost was 200 hr. on SUN SPARC 10 and the error of the predicted threshold voltage was less than 0.02 V.

This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.

This paper describes modeling and simulation of submicron NMOSFET current drive focusing on carrier velocity-saturation effects. A new simple analytical model is proposed which predicts a significant degradation of drain current in sub- and quarter-micron NMOSFET's. Numerical two-dimensional simulations clarify that the degradation is namely caused by high lateral electric field along the channel, which leads to deep velocity-saturation of channel electrons even at the source end. Experimental data of NMOSFET's, with gate oxide thickness (Tox) of 9-20 nm and effective channel lengths (Leff) of 0.35-3.0 µm, show good agreement with the proposed model. It is found that the maximum drain current at the supply voltage of Vdd=3.3 V is predicted to be proportional to Leff0.54 in submicron NMOSFET's, and this is verified with experiments.

Recently, high-dose implantation and low temperature annealing have become one of the key techniques in shallow junction formation. To fabricate shallow junction in quarter-micron CMOS VLSIs, it is well known being important to evaluate the transient enhanced diffusion (TED) of implanted dopants at low temperature furnace annealing, which is caused by the damages of implantation. We have newly studied the TED phenomena by a compact empirical method. This approach has merits of simplicity and better physical intuition, because we can use only minimal parameters to describe the TED phenomena. The other purpose of this work is to evaluate two-dimensional transient enhanced diffusion focusing on phosphorus implant and furnace annealing. Firstly, we defined effective diffusivity of the TED and determined extraction procedure of the model parameters. Number of the TED model parameters is minimized to two, which describe effective enhanced diffusivity and its activation energy. The parameters have been extracted from SIMS profile data obtained from samples which range 1013-31015 cm-2 and 850-950 for phosphorus implanted dose and annealing temperature, respectively. Simulation results with the extracted transient enhanced diffusion parameters show good agreements well with the SIMS data within 2% RMS-error. Critical doses for phosphorus enhanced diffusion have been determined in 950 annealing condition. No transient enhanced diffusion is observed at 950 under the implant dose of 11013 cm-2. Also the transient enhanced diffusivity is leveled off over the dose of 11014 cm-2. It is seen that the critical dose in TED phenomena might be temperature dependent to a certain extent. We have also verified that two-dimensional effect of the TED phenomena experimentally. Two-dimensional phosphorus n- layer is chosen to verify the simulation. It was concluded that the TED has isotropic nature in phosphorus n- diffusion formation.

In MPU and ASIC design with 0.2 µm BiCMOS LSIs, it is well known that interconnect delay becomes one of the key data to ensure high operating frequency. To verify the whole path delay accurately, one needs to create huge delay and waveform libraries which reflect updated process and interconnect structure as well as device performance. Because of the necessity for more than 100 k times of circuit simulation to create the libraries, it was impossible to update the library quickly including process variation effects. In this paper, we have proposed a realistic new method to generate the libraries on the basis of RSM (Response Surface Method). In application for a BiCMOS ASIC process, we have verified that the new method has achieved the reduction of library creation time to 1/100 within the delay error of 3%. This technique can be used in our TCAD and DA framework, which gives a predictive TCAD generation of delay libraries in concurrent ASIC system and process development.