In this paper, a self-recoverable, frequency-aware and cost-effective robust latch (referred to as RFC) is proposed in 45nm CMOS technology. By means of triple mutually feedback Muller C-elements, the internal nodes and output node of the latch are self-recoverable from single event upset (SEU), i.e. particle striking induced logic upset, regardless of the energy of the striking particle. The proposed robust latch offers a much wider spectrum of working clock frequency on account of a smaller delay and insensitivity to high impedance state. The proposed robust latch performs with lower costs regarding power and area than most of the compared latches. SPICE simulation results demonstrate that the area-power-delay product is 73.74% saving on average compared with previous radiation hardened latches.

This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.

A simulation methodology to analyze hot-carrier degradation due to bidirectional stressing in a static RAM circuit has been developed. The bidirectional stressing of pass transistors can approximate to unidirectional stressing. The effective stress direction of each NMOSFET can be determined by the higher of the two junction voltages at the peak substrate current generation. Aged SPICE parameter sets extracted in the forward or in the reverse mode are selected for simulating the degradation of each NMOSFET. Furthermore, effects of each NMOSFET degradation on the degraded circuit behavior are simulated. This technique helps detect an NMOSFET having the largest influence on the circuit aging, improving circuit reliability. The methodology was successfully applied to an SRAM device, and was validated by low temperature bias test data.

Hot-carrier degradation of voltage controlled oscillator (VCO) was investigated by a reliability simulator known as BERT. The appropriate monitor of VCO frequency degradation shifts from the saturated drain current of an N MOSFET to linear drain current with an increase in VCO input voltage. The degradation of the VCO drastically increases with a small reduction in initial oscillation frequency. These results imply the need for an appropriate reliability margin around the standard operating point as well as a performance margin, which cannot be achieved by using conventional drain current monitors.