A switched capacitor DC-DC voltage converter that has an arbitrary conversion ratio of rational number is presented. A given voltage conversion ratio is systematically expanded to construct a switched capacitor circuit that operates with a two-phase switching clock. The conversion ratio is completely free from capacitance values and ratios under the assumption that there is no charge transfer between the two switching phases. This means that the converter cannot supply any power to the load. This restricts the application of the converters to a very limited area such as a voltage reference generator that only provides a reference voltage and no power to a circuit. The conditions for the convergence of the output voltage and the stray capacitor effects are discussed. The output voltage error and required switching frequency are also discussed when the converter is used as a DC voltage supply source that provides power to a load.

In this paper we describe a method for the automated design of analog circuits. The method simultaneously sizes the different components (transistors, capacitors, etc.) in a pre-defined circuit topology and places them according to a pre-defined slicing tree. The method is based on formulating the circuit physical and electrical behavior in a special convex form. More specifically, we cast the design problem as a geometric program, a special type of convex optimization problem. Therefore, all design constraints are formulated as posynomial inequality or monomial equality constraints. Very efficient numerical algorithms are then used to solve the resulting geometric program and to create the design that meets the desired specifications. The formulation is hierarchical and modular, allowing easy topology re-use and process porting. The synthesis method is fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point, and infeasible specifications are unambiguously detected. After a brief overview of current analog design automation solutions, we describe our method and provide some design examples for op-amps and analog-to-digital converters.

A systematic and efficient approach is presented to generating simple yet accurate symbolic expressions for transfer functions and characteristics of large linear analog circuits. The approach is based on a compact determinant decision diagram (DDD) representation of exact transfer functions and characteristics. Several key tasks of generating interpretable symbolic expressions--DDD graph simplification, term de-cancellation, and dominant-term generation--are shown to be able to perform linearly by means of DDD graph operations. An efficient algorithm for generating dominant terms is presented based on the concepts of finding the k-shortest paths in a DDD graph. Experimental results show that our approach outperforms other start-of-the-art approaches, and is capable of generating interpretable expressions for typical analog blocks in minutes on modern computer workstations.

The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.

This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) adders, carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also discusses the CTD-based analysis of carry-propagation-free adders using various number representations.

A C-Ku band 5-bit MMIC phase shifter using optimized reflective series/parallel LC circuits is presented. The proposed circuit has frequency independent characteristics in the case of 180 phase shift, ideally. Also, an ultra-broad-band circuit design theory for the 180 optimized reflective circuit has derived, which gives optimum characteristics compromising between loss and phase shift error. The fabricated 5-bit MMIC phase shifter with SPDT switch has successfully demonstrated a typical insertion loss of 9.4 dB 1.4 dB, and a maximum RMS phase shift error of 7 over the 6 to 18 GHz band. The measured results validate the proposed design theory of the phase shifter.

Two operations, polynomial multiplication and modular reduction, are newly induced by the properties of the modified Booth's algorithm and irreducible all one polynomials, respectively. A new and effective methodology is hereby proposed for computing multiplication over a class of fields GF(2m) using the two operations. Then a low complexity multiplexer-based multiplier is presented based on the aforementioned methodology. Our multiplier consists of m 2-input AND gates, an (m2 + 3m - 4)/2 2-input XOR gates, and m(m - 1)/2 4 1 multiplexers. For the detailed estimation of the complexity of our multiplier, we will expand this argument into the transistor count, using a standard CMOS VLSI realization. The compared results show that our work is advantageous in terms of circuit complexity and requires less delay time compared to previously reported multipliers. Moreover, our architecture is very regular, modular and therefore, well-suited for VLSI implementation.

Delta-sigma modulators (DSMs) are commonly use in high-resolution analog-to-digital converters, and band-pass delta-sigma modulators have recently been used to convert IF signals into digital signals. In particular, a quadrature band-pass delta-sigma modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. The current paper proposes a second-order three-bit quadrature band-pass delta-sigma modulator that can achieve a lower power consumption and better performance with a similar die size to a conventional fourth-order quadrature band-pass delta-sigma modulator (QBPDSM). The proposed system is integrated using CMOS 0.35 µm, double-poly, four-metal technology. The system operates at 13 MHz and can digitize a 200 kHz bandwidth signal centered at 4.875 MHz with an SNR of 85 dB. The power consumption is 35 mW at 3.3 V and 38 mW at 5 V, and the die size is 21.9 mm2.

In this letter, a linear variable resistor circuit using an FG-MOSFET (floating-gate MOSFET) is proposed. This is based on Schlarmann's variable resistor and is very simple. The advantage of the proposed circuit is a wide-input range. The utility of the proposed circuit was confirmed by HSPICE simulation with 1.2 µm CMOS process parameters. The simulation results are reported in this letter.

A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.

This paper proposes a fast multi-cycle path detection method for large sequential circuits. The proposed method is based on ATPG techniques, especially on implication techniques, to use circuit structures and multi-cycle path conditions directly. The method also checks whether or not a multi-cycle path may be invalidated by static hazards at the inputs of flip-flops. Then we explain how to apply the proposed algorithm to real industrial designs. Experimental results show that our method is much faster than conventional ones and that it is efficient enough to handle large industrial designs.

In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method.

Using a level oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model data-path circuits. On the other hand, in order to use such a model for larger circuit, some technique to avoid the state explosion problem is essential. This paper first defines a level oriented formal model based on time Petri nets, and then proposes a partial order reduction algorithm that prunes unnecessary state generation while guaranteeing the correctness of the verification.

In this paper, we propose an alternative method that does not generate a test for each path delay fault directly to generate tests for path delay faults. The proposed method generates an N-propagation test-pair set by using an Ni-detection test set for single stuck-at faults. The N-propagation test-pair set is a set of vector pairs which contains N distinct vector pairs for every transition faults at a check point. Check points consist of primary inputs and fanout branches in a circuit. We do not target the path delay faults for test generation, instead, the N-propagation test-pair set is generated for the transition (both rising and falling) faults of check points in the circuit. After generating tests, tests are simulated to determine their effectiveness for singly testable path delay faults and robust path delay faults. Results of experiments on the ISCAS'85 benchmark circuits show that the N-propagation test-pair sets obtained by our method are effective in testing path delay faults.

A compact Ku-band 5-bit monolithic microwave integrated circuit (MMIC) phase shifter has been demonstrated. The total gate width of switching FETs and the total inductance of spiral inductors are proposed as the figures of merit for compactness. The phase shifter uses the T-type and PI-type high-pass filter (HPF)/band-pass filter (BPF) circuits in which FET "off"-state capacitances are incorporated as the filter elements. According to the figures of merit, the T-type is selected for 90-degree phase shift circuit and the PI-type is selected for the 45-degree phase shift circuit. The fabricated 5-bit phase shifter performs average insertion loss of 5.6 dB and RMS phase shift error of 3.77 degrees with die size of 1.65 mm 0.76 mm (1.25 mm2) in Ku-band.

One-dimentional equivalent circuit model of a heterostructure InAlAs/InGaAs/InP metal-semiconductor-metal photodetector is discussed. In this photodetector, InGaAs is used as an optical absorption layer and the InAlAs is used for Schottky barrier enhanement. The measured S11 parameter deviates from equi-resistance lines on the Smith chart, indicating the equivalent circuit is different from the conventional equivalent circuit using a series resistance, a depletion region capacitance and a depletion region resistance. The difference is due to band discontinuity at the heterojunctions, and we propose a equivalent circuit taking account of the band discontinuity. The band discontinuity is expressed by parallel combination of a resistance and a capacitance. The measured S11 parameter can be fitted well with the calculated S11 parameter from the proposed equivalent circuit, and we can successfully extract the device parameters from the fitted curve.

Field-theoretical equivalent circuit models of a variety of coplanar waveguide (CPW) lumped-element discontinuities for two dominant modes are characterized by executing the short-open calibration (SOC) procedure in the fullwave method of moments (MoM). In our developed MoM platform, the impressed current sources with even or odd symmetry are introduced at the selected ports in order to separately excite the even and odd dominant modes, i.e., CPW- and CSL-mode. After the port network parameters are numerically derived using the Galerkin's technique, the two SOC standards are defined and evaluated in the self-consistent MoM to effectively de-embed and extract the core model parameters of a CPW circuit or discontinuity. After the validation is confirmed via comparison with the published data, extensive investigation is carried out to for the first time demonstrate the distinctive model properties of one-port CPW short- and open-end elements as well as two-port inductive and capacitive coupling elements with resorting to its two different dominant modes.

We study the advantages and limitations of InP/GaAsSb/InP DHBTs for high-speed digital circuit applications. We show that the high-current performance limitation in these devices is electrostatic in nature. Comparison of the location of collector current blocking in various collector designs suggests a smoother, more gradual onset of blocking effects in type-II collectors. A comparison of collector current blocking effects between InP/GaAsSb--based and various designs of InP/GaInAs--based DHBTs provides support for our analysis.

A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 µm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.

This paper proposes an analytical expression for the maximum operating frequency of an emitter-coupled-logic master-slave toggle flip-flop (ECL MS TFF) based on an impulse response method. The analytical expression was in good agreement with not only SPICE simulations, but also experimental values. The analytical expression also indicated that state-of-the-art InP-based heterojunction bipolar transistors have potential to achieve over 100-GHz operation in ECL MS TFFs. Also, the proposed method was applied to the maximum operating frequency of a source-coupled FET logic (SCFL) MS TFF.