A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier
Summary :
A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 µm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.10 pp.2122-2128
- Publication Date
- 2003/10/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
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Cheng-Chung HSU, Jieh-Tsorng WU, "A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 10, pp. 2122-2128, October 2003, doi: .
Abstract: A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 µm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_10_2122/_p
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@ARTICLE{e86-c_10_2122,
author={Cheng-Chung HSU, Jieh-Tsorng WU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier},
year={2003},
volume={E86-C},
number={10},
pages={2122-2128},
abstract={A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 µm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.},
keywords={},
doi={},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier
T2 - IEICE TRANSACTIONS on Electronics
SP - 2122
EP - 2128
AU - Cheng-Chung HSU
AU - Jieh-Tsorng WU
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2003
AB - A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 µm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.
ER -
English
