A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG
Summary :
A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3072-3078
- Publication Date
- 2003/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Timing Verification and Test Generation
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Hideyuki ICHIHARA, Tomoo INOUE, "A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 12, pp. 3072-3078, December 2003, doi: .
Abstract: A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3072/_p
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@ARTICLE{e86-a_12_3072,
author={Hideyuki ICHIHARA, Tomoo INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG},
year={2003},
volume={E86-A},
number={12},
pages={3072-3078},
abstract={A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3072
EP - 3078
AU - Hideyuki ICHIHARA
AU - Tomoo INOUE
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort.
ER -
English
