In this paper, we propose a universal biquad filter that can realize all types of 2nd-order functions, such as Low-pass Filters (LPF), High-Pass Filters (HPF), Band-Pass Filters (BPF), Band-Elimination Filters (BEF), and All-Pass Filters (APF). Also, the filter types can be programmable digitally with built-in switches. The proposed circuit can be realized by using a CMOS technology that is suitable for a mixed digital-analog LSI. In addition, the circuit can operate in high frequencies with a low power supply voltage because it is based on a current-mode circuit. Finally, the proposed circuit is simulated by PSpice to confirm its characteristics.

This paper proposes a new method for image segmentation and extraction using nonlinear cellular networks. Flexible segmentation of complicated natural scene images is achieved by using resistive-fuse networks, and each segmented regions is extracted by nonlinear oscillator networks. We also propose a nonlinear cellular network circuit implementing both resistive-fuse and oscillator dynamics by using pulse-modulation techniques. The basic operation of the nonlinear network circuit is confirmed by SPICE simulation. Moreover, the 1010-pixel image segmentation and extraction are demonstrated by high-speed circuit simulation.

In this report, we propose a new bilateral floating resistor circuit having both positive and negative resistance values. The equivalent resistance of this floating resistor in CMOS technology can be changed by using controlled-voltages, which is an advantage over polysilicon or diffused resistor in the integrated circuit. Moreover the characteristics of the proposed circuit are independent of the threshold voltage. We have simulated the proposed circuit by using HSPICE. Finally, we have confirmed that the proposed circuit is useful as an analog component.

A 2-GHz down-converter for wide-band wireless communication systems is described. To achieve both wide-band output characteristic and LO signal suppression, an on-chip LC series resonator which is resonated at LO signal frequency and a transimpedance amplifier which is used in the output buffer circuit are used. To achieve a low sensitivity to temperature, two kinds of bias circuits; a VT reference current source and a bandgap reference current source are used. The measured 3-dB bandwidth of 600 MHz is achieved. The conversion gain varies less than 0.2 dB within 200 MHz 10 MHz and 400 MHz 10 MHz band and 0.7 dB for the temperature range from -34 to 85. At room temperature, conversion gain of 15 dB, NF of 9.5 dB and IIP3 of -5 dBm are obtained respectively. The down-converter is fabricated using Si BiCMOS process with ft=20 GHz, and it occupies approximately 1 mm2.

This letter presents a novel application of the Verilog-A, which is a hardware description language for analog circuits, to the modeling and simulation of high-speed interconnects in time/frequency transform-domain for signal integrity problems. This modeling method with the Verilog-A language would handle the transfer function approximation and admittance matrices, which are expressed by the dominant poles and residues as used in AWE technique. Finally, it is shown that modeling and simulation of the high-speed interconnects with nonlinear terminations can be done easily.

Finding DC operating-points of nonlinear circuits is an important and difficult task. The Newton-Raphson method employed in the SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. The fixed-point homotopy method is one of the excellent methods. However, from the viewpoint of implementation, it is important to study it further so that the method can be easily and widely used by many circuit designers. This paper presents a practical method to implement the fixed-point homotopy method. A special circuit called the solution-tracing circuit for the fixed-point homotopy method is proposed. By using this circuit, the solution curves of homotopy equations can be traced by performing the SPICE transient analysis. Therefore, no modification to the existing programs is necessary. Moreover, it is proved that the proposed method is globally convergent. Numerical examples show that the proposed technique is effective and can be easily implemented. By the proposed technique, many SPICE users can easily implement the fixed-point homotopy method.

A high isolation hybrid circuit composed of a pair of transformers, a voltage control resistance (VCR) circuit and an automatic impedance control device is designed for a two-wire full duplex cable modem to adapt variable line impedance. A binary frequency shift keying (BFSK) cable modem using the new hybrid circuit with an isolation of 52 dB to 58 dB in the line impedance variation range of 400 to 950 ohm is demonstrated. The isolation of the new hybrid circuit is increased by more than 30 dB over the traditional hybrid circuit for a two-wire full duplex modem in the preset line impedance range.

In this paper, four coupled chaotic circuits generating four-phase quasi-synchronization of chaos are proposed. By tuning the coupling parameter, chaotic wandering over the phase states characterized by the four-phase synchronization occurs. In order to analyze chaotic wandering, dependent variables corresponding to phases of solutions in subcircuits are introduced. Combining the variables with hysteresis decision of the phase states enables statistical analysis of chaotic wandering.

To overcome the problems of the modified Dickson pump like NCP-2, another pump (CCTS-1) where simple voltage doublers are cascaded in series and each of them has cross-coupled configuration is studied in this letter for possible use in low-voltage EEPROMs and DRAMs. Though this concept of cascading doublers has been previously proposed, it is firstly addressed in this letter that CCTS-1 has lower gate-oxide stress, improved voltage pumping gain, and better power efficiency than NCP-2 so that CCTS-1 can be more suitable for multi-stage pump in particular at low VCC. In addition, CCTS-2 is proposed to overcome the degraded body-effect of CCTS-1 without using boosted clocks when the stage number is large.

This paper describes how the symmetry of a three-phase circuit prevents the symmetric modes of several subharmonic oscillations. First, we make mathematically it clear that the generation of symmetrical 1/3l-subharmonic oscillations (l=1,2,) are impossible in the three-phase circuit. As far as 1/(3l+1)-subharmonic oscillations (l=1,2,) and 1/(3l+2)-subharmonic oscillations (l=0,1,) are concerned, the former in negative-phase sequence and the latter in positive-phase sequence are shown to be impossible. Further, in order to confirm the above results, we apply the method of interval analysis to the circuit equations and obtain all steady state solutions with unsymmetric modes.

This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.

An automated analog circuit synthesis based on reuse of topological features of 'prototype circuits' is proposed. The prototype circuits are designed by humans and suggested to the synthesis system as hints of configurations of new analog circuits to be synthesized by the system. The connections of elements in analog circuits are not generally systematic, but they would have some similarities to a circuit which has similar behaviors or functionalities. In the proposed process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. And then, genetic algorithm is used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are performed with a novel technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through an example of the synthesis.

This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.

In this paper, we present a new algorithm for statistical static timing analysis of a CMOS combinatorial circuit, which takes correlations into account to improve accuracy of the distribution of the maximum delay of the circuit. The correlations treated in the algorithm are not only the one between distributions of arrival times of input signals to a logic gate but also correlation between switching delays of a logic gate and correlation between interconnect delays of a net. We model each delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the maximum of two delays. Since the algorithm takes the correlation into account, the time complexity is O(m2) in the worst-case, where m is the number of edges of the graph representing a given circuit. But, for real combinatorial circuits, the complexity is expected to be less than this.

This paper introduces current-mode biquad using multiple current output operational transconductance amplifiers (OTAs) and grounded capacitors. The circuit configuration is obtained from a second-order integrator loop structure with loss-less and lossy integrators. The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by suitably choosing the input and output terminals. And the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. It is also made clear that the proposed circuit has very low sensitivities with respect to the circuit active and passive elements. An example is given together with simulated results by PSpice.

This paper proposes a multisegment dielectric resonator (MSDR) placed on a slotline for millimeter-wave filter applications. The MSDR structure, including a rectangular dielectric lump and a thin low-dielectric insert, is quite useful for adjusting the coupling between the slotline mode and the resonant mode, leading to improve the filter performances. In addition, by tuning dimensions of the MSDR, a sharp and clear notch response can be designed in the transmission parameter. We have demonstrated the filter characteristics both theoretically and experimentally, and showed the practical procedure for the design of MSDR filters.

The temperature compensation technique of InGaP/GaAs power heterojunction bipolar transistor (HBT) with novel bias circuit using Schottky diodes has been developed. The variation in the quiescent current to the temperature is less than 30% from -30C to 90C by this technique, where that is about 125% by the conventional bias circuit. The RF performance of the power HBT MMIC with novel bias circuit shows flat temperature characteristics enough to be used for power application of wireless communications.

Although TE0nδ mode ceramic resonators are usually used at centimeter frequencies, they have difficulty in making wide-band band-pass filters in the millimeter-wave region due to the weak coupling factors between TE0nδ mode resonators and input/output waveguides. In order to overcome such difficulty, a band-widening technique of the ceramic resonator loaded band-pass filter has been proposed. The EHnmδ modes were regarded as spurious modes so far, but it is clear that the coupling factors are larger than those of the TE0nδ modes from the results of experimental considerations in this paper. By using the EH11δ mode ceramic resonators, 5-pole, 1 dB Chebyshev ripple NRD guide band-pass filter has been fabricated for the applications to broad-band millimeter-wave communication systems at 60 GHz. The filter has great advantages such as the wide pass-band beyond 2 GHz and low excess insertion loss of less than 0.3 dB.

This paper presents an automatic synthesis method of active analog circuits that uses evolutionary search and employs some topological features of analog integrated circuits. Our system firstly generates a set of circuits at random, and then evolves their topologies and device sizing to fit an environment which is formed by the fitness function translated from the electrical specifications of the circuit. Therefore expert knowledge about circuit topologies and sizing are not needed. The capability of this method is demonstrated through experiments of automatic synthesis of CMOS operational amplifiers.