IEICE TRANSACTIONS on Fundamentals
Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis--
Summary :
This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.11 pp.2808-2810
- Publication Date
- 2001/11/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Analog Synthesis
Authors
Keyword
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Masanori NATSUI, Takafumi AOKI, Tatsuo HIGUCHI, "Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis--" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2808-2810, November 2001, doi: .
Abstract: This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2808/_p
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@ARTICLE{e84-a_11_2808,
author={Masanori NATSUI, Takafumi AOKI, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis--},
year={2001},
volume={E84-A},
number={11},
pages={2808-2810},
abstract={This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis--
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2808
EP - 2810
AU - Masanori NATSUI
AU - Takafumi AOKI
AU - Tatsuo HIGUCHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through experimental synthesis of a radix-4 signed-digit (SD) full adder circuit.
ER -
English
