In this paper, a self optimization beamforming null control (SOBNC) scheme is proposed. There is a need of maintaining signal to interference plus noise ratio (SINR) threshold to control modulation and coding schemes (MCS) in recent technologies like Wi-Fi, Long Term Evolution (LTE) and Long Term Evolution Advanced (LTE-A). Selection of MCS depends on the SINR threshold that allows maintaining key performance index (KPI) like block error rate (BLER), bit error rate (BER) and throughput at certain level. The SOBNC is used to control the antenna pattern for SINR estimation and improve the SINR performance of the wireless communication systems. The nulling comes with a price; if wider nulls are introduced, i.e. more number of nulls are used, the 3dB beam-width and peak side lobe level (SLL) in antenna pattern changes critically. This paper proposes a method which automatically controls the number of nulls in the antenna pattern as per the changing environment based on adaptive-network based fuzzy interference system (ANFIS) to maintain output SINR level higher or equal to the required threshold. Finally, simulation results show a performance superiority of the proposed SOBNC compared with minimum mean square error (MMSE) based adaptive nulling control algorithm and conventional fixed null scheme.

For the purpose of reducing the quantization noise and power consumption of UWB-OFDM transceiver, a new time domain-based interpolator and decimator structure is proposed to realize five-bit D/A and A/D converters in the five-bit 128-tone sigma-delta modulation (SDM) UWB-OFDM transceiver. The five-bit 128-tone SDM UWB-OFDM transceiver using time domain-based interpolator and decimator in place of time spreader and de-spreader can obtain time-domain spread spectrum processing gain and reduce quantization noise simultaneously. The structure of the five-bit 128-tone SDM A/D converter, which employs 32 parallel analog SDM circuits without up-sampling, is designed. Simulation results demonstrate that BER of the proposed five-bit 128-tone SDM D/A and A/D converters based on time domain-based interpolator and decimator scheme can satisfy the performance requirements of the five-bit 128-tone SDM UWB-OFDM transceiver for the QPSK, 16-QAM and 64-QAM modulations.

An adaptive rate controller (ARC) based on an adaptive neural fuzzy inference system (ANFIS) is designed to autonomously adjust the data rate of a mobile heterogeneous network to adapt to the changing traffic load and the user speed for multimedia call services. The effect of user speed on the handoff rate is considered. Through simulations, it has been demonstrated that the ANFIS-ARC is able to maintain new call blocking probability and handoff failure probability of the mobile heterogeneous network below a prescribed low level over different user speeds and new call origination rates while optimizing the average throughput. It has also been shown that the mobile cognitive wireless network with the proposed CS-ANFIS-ARC protocol can support more traffic load than neural fuzzy call-admission and rate controller (NFCRC) protocol.

A high isolation hybrid circuit composed of a pair of transformers, a voltage control resistance (VCR) circuit and an automatic impedance control device is designed for a two-wire full duplex cable modem to adapt variable line impedance. A binary frequency shift keying (BFSK) cable modem using the new hybrid circuit with an isolation of 52 dB to 58 dB in the line impedance variation range of 400 to 950 ohm is demonstrated. The isolation of the new hybrid circuit is increased by more than 30 dB over the traditional hybrid circuit for a two-wire full duplex modem in the preset line impedance range.

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.