IEICE TRANSACTIONS on Information
Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF
Summary :
The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.
- Publication
- IEICE TRANSACTIONS on Information Vol.E95-D No.2 pp.413-425
- Publication Date
- 2012/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E95.D.413
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Application
Authors
Keyword
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Jeich MAR, Chi-Cheng KUO, Shin-Ru WU, You-Rong LIN, "Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF" in IEICE TRANSACTIONS on Information,
vol. E95-D, no. 2, pp. 413-425, February 2012, doi: 10.1587/transinf.E95.D.413.
Abstract: The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E95.D.413/_p
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@ARTICLE{e95-d_2_413,
author={Jeich MAR, Chi-Cheng KUO, Shin-Ru WU, You-Rong LIN, },
journal={IEICE TRANSACTIONS on Information},
title={Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF},
year={2012},
volume={E95-D},
number={2},
pages={413-425},
abstract={The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.},
keywords={},
doi={10.1587/transinf.E95.D.413},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF
T2 - IEICE TRANSACTIONS on Information
SP - 413
EP - 425
AU - Jeich MAR
AU - Chi-Cheng KUO
AU - Shin-Ru WU
AU - You-Rong LIN
PY - 2012
DO - 10.1587/transinf.E95.D.413
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2012
AB - The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.
ER -
English
