For the purpose of reducing the quantization noise and power consumption of UWB-OFDM transceiver, a new time domain-based interpolator and decimator structure is proposed to realize five-bit D/A and A/D converters in the five-bit 128-tone sigma-delta modulation (SDM) UWB-OFDM transceiver. The five-bit 128-tone SDM UWB-OFDM transceiver using time domain-based interpolator and decimator in place of time spreader and de-spreader can obtain time-domain spread spectrum processing gain and reduce quantization noise simultaneously. The structure of the five-bit 128-tone SDM A/D converter, which employs 32 parallel analog SDM circuits without up-sampling, is designed. Simulation results demonstrate that BER of the proposed five-bit 128-tone SDM D/A and A/D converters based on time domain-based interpolator and decimator scheme can satisfy the performance requirements of the five-bit 128-tone SDM UWB-OFDM transceiver for the QPSK, 16-QAM and 64-QAM modulations.

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.