We describe hybrid integration technologies that employ silica-based planar lightwave circuit (PLC) platforms, and report several high-performance optical components based on these technologies. First, we describe the requirements for optical integrated circuits. Then, we discuss the technologies used in hybrid integration, namely optical coupling between a semiconductor optical device and a silica waveguide, electrical signal transmission to the semiconductor optical device, and high quality optical signal processing. In addition, we describe optical integrated circuits developed for short- and long-haul networks. We realized these high-performance integrated components by combining appropriate hybrid integration technologies.

We theoretically and experimentally demonstrate low loss branches in a Si photonic wire waveguide. Approximate calculation by the two-dimensional finite-difference time-domain (2-D FDTD) method and detailed design by the 3-D FDTD method indicate that low excess loss less than 0.2 dB is expected for a µm-size bend-waveguide-type branch at a wavelength of 1.55 µm. This branch is fabricated in a silicon-on-insulator substrate and the loss is evaluated to be 0.3 dB. This value is small enough to construct a very compact branching circuit.

At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating trade-off between power and area/delay by applying gated clocks is very important. In this paper, we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks. The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.

We propose a set of Fabry-Perot etalons integrated in a planar lightwave circuit (PLC-FPE) designed for a unified system for broadcasting and communication. A PLC-FPE containing four etalons having different cavity lengths is fabricated and their loss and frequency characteristics are investigated. The total loss and the maximum finesse were found to be 8 dB and 34, respectively.

A digital circuit technique is proposed to process directly bit-stream signals from analog-to-digital converters based on sigma-delta modulation. Newly developed adder and multiplier are fundamental circuit modules for the processing. Using the fundamental modules and up/down counters, other circuit modules such as divider and square root circuits are also realized. The signal processors built of the modules have advantages over multi-bit Nyquist rate processors in circuit scale by the following two distinct features: First, single-bit/multi-bit converters are not needed at the inputs of the processors because the arithmetic modules directly process bit-stream signals. Secondly, the arithmetic modules consist of small number of logic gates. As an application of the technique to digital signal processing for communications, a QPSK demodulator is presented. The demodulator is structured with 40% of logic gates consumed by an equivalent multi-bit demodulator.

In this paper, we propose an improved network-flow based multi-way circuit partitioning algorithm whose objective is to minimize the number of sub-circuits. It iteratively extracts a size-maximal feasible sub-circuit one at a time. In our approach, two devices are applied. One is in the use of an exact min-cut graph, and the other is in the idea of keeping the number of I/O pins of the residual circuit as small as possible after one-time extraction. We implemented our algorithm in C for experiments, and tested it with several industrial cases and MCNC benchmarks. Compared to the known approach, we observed more than 10% reduction in average of the sub-circuit number.

We fabricated ramp-edge junctions with barriers by modifying surface and integrating ground-planes. The fabricated junctions had current-voltage characteristics consistent with the resistive shunted-junction model. We also obtained a 1-sigma spread in the critical current of 7.9% for 100 junctions at 4.2 K. The ground-plane reduced the sheet inductance of a stripline by a factor of 3. The quality of the ground-plane was improved by using an anneal in oxygen atmosphere after fabrication. The sheet inductance of a counter-electrode with a ground-plane was 1.0 pH per square at 4.2 K.

In this paper, we describe our SFQ circuit design and measurement carried out in SRL-ISTEC. We are studying an oversampling sigma-delta modulator and a counter-type decimation filter with multistage structure for developing AD converters for software-defined radio application. We are also developing a superconducting memory, whose peripheral circuits are constructed with SFQ circuits.

We describe the width conversion of an optical signal by using an erbium-doped fiber and an asymmetric optical circuit. The width of an optical signal was measured to be a respective 350 nsec and 200 nsec for a 70 m and 40 m fiber (Lf). The width of the pumping pulse was 5 nsec and the length of erbium-doped fiber was 3 m. We also extended the optical signals to a respective 300 nsec and 150 nsec wide at a pumping pulse 10 nsec by inserting a 60 m and a 30 m fiber (Lf) inside a circuit.

In this paper, we study the fundamental combinatorial nonlinear resonances of a system consisting of two identical periodic forced circuits coupled by a linear resistor. The circuit equations are described by a system of coupled Duffing's equations. We discuss two cases of external periodic force, i.e., in-phase and anti-phase, and obtain the bifurcation diagram of each case. Periodic solutions are classified according to the symmetrical property of the circuit. Resonances in the coupled system are explained from the combinatorial standpoint. That is, we introduce the definition of combinatorial resonances and investigate the patterns of combinatorial solutions in this system.

In this paper, we report a study on hardware implementation of a Deterministic Boltzmann Machine (DBM) with non-monotonic neurons (non-monotonic DBM network). The hardware DBM network has fewer components than other neural networks. Results from numerical simulations show that the non-monotonic DBM network has high learning ability as compared to the monotonic DBM network. These results show that the non-monotonic DBM network has large potential for the implementation of a high functional neurochip. Then, we design and fabricate a neurochip of the non-monotonic DBM network of which measurement confirms that the high-functional large-scale neural system can be realized on a compact neurochip by using the non-monotonic neurons.

We have proposed a top-down design methodology for the RSFQ logic circuits based on the Binary Decision Diagram (BDD). In order to show the effectiveness of the methodology, we have designed a small RSFQ microprocessor based on simple architecture. We have compared the performance of the 8-bit RSFQ microprocessor with its CMOS version. It was found that the RSFQ system is superior in terms of the operating speed though it requires extremely large area. We have also implemented and tested a 1-bit ALU that is one of the important components of the microprocessor and confirmed its correct operation.

This article describes simulation study on SQUID applications for Single-Flux-Quantum(SFQ) Logic Circuits. Here, a SQUID is compatible to a Quantum Flux Parametorn (QFP). Several new circuits based on a SQUID are investigated. A cascaded SQUID is proposed with the signal amplitude in the same order of an SFQ. An SFQ-pulse driving circuits with the new SQUID are successfully simulated. An SFQ trap which catches SFQs is newly proposed. Focusing on a circulating current of a segment in a Josephson transmission line (JTL), an SFQ-pulse is non-destructively detected by a SQUID. A conventional SQUID inserted in a JTL operates as a gate which controls SFQ-pulse transmission through it. Compatibility of SQUIDs and SFQ circuits is demonstrated.

High-end telecommunication systems in the larger nationwide networks of the next decade will require routers having a packet switching throughput capacity of over 10 Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. We propose a high-end router system architecture using single flux quantum (SFQ) technology. This system consists of semiconductor line card units and an SFQ switch card unit. The features of this switch card architecture are (1) using internal speedup architecture to reduce effective loads in the network, (2) using a packet switch scheduler to attain non-blocking characteristics. This architecture can expand the switching capacity to a level greater than tens of Tbps scale, keeping with non-blocking characteristics.

We present a design framework of a high-end server based on Single-Flux-Quantum (SFQ) circuit technologies. The server proposed here has multiple microprocessors and memories, which are mounted on a single board or package and are connected each other by SFQ interconnection switches. The extremely large bandwidth up to 100 Gbps/channel in the interconnection will be realized because of high throughput nature of the SFQ circuits. SFQ memories or Josephson-CMOS hybrid memories are employed as the shared memory of the multiprocessor. The SFQ microprocessors are constructed based on the complexity-reduced (CORE) architecture, in which complexity of the system is eased in exchange for using a high clock rate of the SFQ circuits. The processor is so-called Java-processor that directly executes the Java Byte Codes. Assuming a proper advancement of the Nb/AlOx/Nb integrated circuit process technology, we have estimated that the power consumption of the server system including a cryocooler is reduced by a factor of twenty as compared to the future CMOS system with the same processor performance, while the SFQ system has 100 times of magnitude larger memory-processor bandwidth.

This paper describes a simple design of a broad-band four-way power divider with 45-degree phase differences between output ports. In the first stage of our work, we present a new broad-band 90-degree power divider. The phase error of the power divider here is less than one-tenth of the conventional 90-degree branch-line hybrid. Next, an experimental UHF-band four-way power divider using a broad-band 90-degree power divider and two broad-band 45-degree power dividers is presented. Over the frequency range from 0.86 to 1.06 GHz, the experimental four-way power divider exhibits power splits of -6.420.25 dB, return losses of greater than 15 dB, errors in the desired relative-phase difference between output ports of less than 1 degree, and isolation between output ports of greater than 15 dB. This divider is useful for realizing low distortion and high efficiency amplifiers without the need for an isolator.

We describe the logic design of a single-flux-quantum (SFQ) 22 unit switch. It is the main component of the SFQ Banyan packet switch we are developing that enables a switching capacity of over 1 Tbit/s. In this paper, we focus on the design of the controller in the unit switch. The controller does not have a simple "off-the-shelf" conventional circuit, like those used in shift registers or adders. To design such a complicated random logic circuit, we need to adopt a systematic top-down design approach. Using a graphical technique, we first obtained logic functions. Next, to use the deep pipeline architecture, we broke down the functions into one-level logic operations that can be executed within one clock cycle. Finally, we mapped the functions on to the physical circuits using pre-designed SFQ standard cells. The 22 unit switch consists of 59 logic gates and needs about 600 Josephson junctions without gate interconnections. We tested the gate-level circuit by logic simulation and found that it operates correctly at a throughput of 40 GHz.

We present the design of dual rail Data Driven Self Timed (DDST) DEMUX and MUX circuits for 50 GHz operation. The chosen current density is 6.5 kA/cm2 and simulations show good margins for speeds exceeding 50 GHz. Our previously reported dual-rail on-chip test system is also scaled up for 50 GHz operation.

In this report, we propose a new bilateral floating resistor circuit having both positive and negative resistance values. The equivalent resistance of this floating resistor in CMOS technology can be changed by using controlled-voltages, which is an advantage over polysilicon or diffused resistor in the integrated circuit. Moreover the characteristics of the proposed circuit are independent of the threshold voltage. We have simulated the proposed circuit by using HSPICE. Finally, we have confirmed that the proposed circuit is useful as an analog component.

This letter presents a novel application of the Verilog-A, which is a hardware description language for analog circuits, to the modeling and simulation of high-speed interconnects in time/frequency transform-domain for signal integrity problems. This modeling method with the Verilog-A language would handle the transfer function approximation and admittance matrices, which are expressed by the dominant poles and residues as used in AWE technique. Finally, it is shown that modeling and simulation of the high-speed interconnects with nonlinear terminations can be done easily.