IEICE TRANSACTIONS on Fundamentals
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks
Summary :
At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating trade-off between power and area/delay by applying gated clocks is very important. In this paper, we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks. The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.
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- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.4 pp.827-834
- Publication Date
- 2002/04/01
- Publicized
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- Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
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Shinichi NODA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, "High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 4, pp. 827-834, April 2002, doi: .
Abstract: At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating trade-off between power and area/delay by applying gated clocks is very important. In this paper, we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks. The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_4_827/_p
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@ARTICLE{e85-a_4_827,
author={Shinichi NODA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks},
year={2002},
volume={E85-A},
number={4},
pages={827-834},
abstract={At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating trade-off between power and area/delay by applying gated clocks is very important. In this paper, we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks. The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 827
EP - 834
AU - Shinichi NODA
AU - Nozomu TOGAWA
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2002
AB - At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating trade-off between power and area/delay by applying gated clocks is very important. In this paper, we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks. The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.
ER -
English
