Utilizing the enormous potential of quantum computers requires new and practical quantum algorithms. Motivated by the success of machine learning, we investigate the fusion of neural and quantum computing, and propose a learning method for a quantum neural network inspired by the Hebb rule. Based on an analogy between neuron-neuron interactions and qubit-qubit interactions, the proposed quantum learning rule successfully changes the coupling strengths between qubits according to training data. To evaluate the effectiveness and practical use of the method, we apply it to the memorization process of a neuro-inspired quantum associative memory model. Our numerical simulation results indicate that the proposed quantum versions of the Hebb and anti-Hebb rules improve the learning performance. Furthermore, we confirm that the probability of retrieving a target pattern from multiple learned patterns is sufficiently high.

There is increasing interest in quantum computing, because of its enormous computing potential. A small number of powerful quantum algorithms have been proposed to date; however, the development of new quantum algorithms for practical use remains essential. Parallel computing with a neural network has successfully realized certain unique functions such as learning and recognition; therefore, the introduction of certain neural computing techniques into quantum computing to enlarge the quantum computing application field is worthwhile. In this paper, a novel quantum associative memory (QuAM) is proposed, which is achieved with a quantum neural network by employing adiabatic Hamiltonian evolution. The memorization and retrieval procedures are inspired by the concept of associative memory realized with an artificial neural network. To study the detailed dynamics of our QuAM, we examine two types of Hamiltonians for pattern memorization. The first is a Hamiltonian having diagonal elements, which is known as an Ising Hamiltonian and which is similar to the cost function of a Hopfield network. The second is a Hamiltonian having non-diagonal elements, which is known as a neuro-inspired Hamiltonian and which is based on interactions between qubits. Numerical simulations indicate that the proposed methods for pattern memorization and retrieval work well with both types of Hamiltonians. Further, both Hamiltonians yield almost identical performance, although their retrieval properties differ. The QuAM exhibits new and unique features, such as a large memory capacity, which differs from a conventional neural associative memory.

In this paper, we report a study on hardware implementation of a Deterministic Boltzmann Machine (DBM) with non-monotonic neurons (non-monotonic DBM network). The hardware DBM network has fewer components than other neural networks. Results from numerical simulations show that the non-monotonic DBM network has high learning ability as compared to the monotonic DBM network. These results show that the non-monotonic DBM network has large potential for the implementation of a high functional neurochip. Then, we design and fabricate a neurochip of the non-monotonic DBM network of which measurement confirms that the high-functional large-scale neural system can be realized on a compact neurochip by using the non-monotonic neurons.

The utilization of a high-Tc superconductor for implementing a superconducting qubit is to be expected. Recent researches on the quantum property of Josephson junctions in high-Tc superconductors indicate that the low energy quasiparticle excitation is weak enough to observe the macroscopic quantum tunneling. Therefore, a detailed study on the quantum property of high-Tc Josephson junctions becomes more important for applications. We show our experimental results of the macroscopic tunneling of current biased intrinsic Josephson junctions in Bi-2212 and its resonant activation in the presence of microwave radiation.

Majority logic is quite important for various applications such as fault tolerant systems, threshold logic, spectrum spread coding, and artificial neural networks. The circuit implementation of majority logic is difficult when the number of inputs becomes large because the number of transistors becomes huge and serious delay would occur. In this paper, we propose a new majority circuit with large fan-in. The circuit is composed of ordinary CMOS transistors and the total number of transistors is approximately only 4N, where N is the total number of inputs. We confirmed a correct operation by using HSPICE simulation. The yield of the proposed circuit was evaluated with respect to N under the variations of device parameters by using Monte Carlo simulation.

We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.

Single electron devices are ultra low power and extremely small devices, and suitable for implementation of large scale integrated circuits. Artificial neural networks (ANNs), which require a large number of transistors for being to be applied to practical use, is one of the possible applications of single electron devices. In order to simplify a single electron circuit configuration, we apply stochastic logic in which various complex operations can be done with basic logic gates. We design basic subcircuits of a single electron stochastic neural network, and confirm that backgate bias control and a redundant configuration are necessary for a feedback loop configuration by computer simulation based on Monte Carlo method. The proposed single electron circuit is well-suited for hardware implementation of a stochastic neural network because we can save circuit area and power consumption by using a single electron random number generator (RNG) instead of a conventional complementary metal oxide semiconductor (CMOS) RNG.

The hardware implementation of a neural network model using stochastic logic has been able to integrate numerous neuron units on a chip. However, the limitation of applications occurred since the stochastic neurosystem could execute only discrete-time dynamics. We have contrived a neuron model with continuous-time dynamics by using stochastic calculations. In this paper, we propose the circuit design of a new neuron circuit, and show the fabricated neurochip comprising 64 neurons with experimental results. Furthermore, a new asynchronous updating method and a new activation function circuit are proposed. These improvements enhance the performance of the neurochip greatly.

The effects of α-particle-induced parasitic bipolar current on soft errors in submicron 6-transistor SOI SRAMs were numericaly studied. It was shown that the bipolar current induces soft errors and that there exists a critical quantity which determines the soft error occurrence in the SOI SRAMs. Simulated soft error rates were in the same order as those for bulk SRAMs.

A chaotic noise is one of the most important implements for information processing such as neural networks. It has been suggested that chaotic neural networks have high performance ability for information processing. In this paper, we report two designs of a compact chaotic noise generator for large integration circuits using CMOS technology. The chaotic noise is generated using map chaos. We design both of the logistic map type and the tent map type circuits. These chaotic noise generators are compact as compared with the other circuits. The results show that the successful chaotic operations of the circuits because of the positive Lyapunov number. We calculate the Lyapunov exponents to certify the results of the chaotic operations. However, it is hard to estimate its accurate number for noisy data using the conventional method. And hence, we propose the modified calculation of the Lyapunov exponent for noisy data. These two circuits are expected to be utilized for various applications.

We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural system. We use a 4-bit SRAM as the memory for synaptic weights. The expected I/O characteristics of the neurons and the synapses were measured experimentally. We have also demonstrated the capability of network operation with the use of synaptic weights, for solving the A/D conversion problem.

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called "switched diffusion analog memory with feedback circuit (FBSDAM). " FBSDAM has linear writing and erasing characteristics. Therefore, FBSDAM is useful for memorizing an analog value exactly. We also propose a new analog content-addressable memory (CAM) which has neural-like learning and discriminating functions which discriminate whether an incoming pattern is an unknown pattern or a stored pattern. We design and fabricate the CAM using FBSDAM by means of the 4µm double-poly single-metal CMOS process and nonvolatile analog memory technology which are developed by us. The chip size is 3.1 mm3.1 mm. We estimate that the CAM is composed of 50 times fewer transistors and requires 70 times fewer calculation steps than a typical digital computer implemented using similar technology.

We have fabricated a new analog memory with a floating gate as a key component to store synaptic weights for integrated artificial neural networks. The new analog memory comprises a tunnel junction (poly-Si/poly-si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating gate MOSFET. The diffusion of the charges injected through the tunnel junction is controlled by switching operation of the thin-film transistor, and we refer to the new analog memory as switched diffusion analog memory (SDAM). The obtained characteristics of SDAM are a fast switching speed and an improved linearity between the potential of the floating gate and the number of pulse inputs. SDAM can be used in a neural network in which write/erase and read operations are performed simultaneously.

A random number generator composed of single electron devices is presented. Due to stochastic behavior of electron tunneling process, single electron devices have intrinsic randomness. Using its randomness, a true random number generator can be implemented. Although fluctuation of device parameters degrades the performance of the proposed circuit, we show that the adjustment of the bias voltages can compensate the fluctuation.

In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.