IEICE TRANSACTIONS on Information
Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic
Summary :
In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.
- Publication
- IEICE TRANSACTIONS on Information Vol.E89-D No.9 pp.2572-2578
- Publication Date
- 2006/09/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e89-d.9.2572
- Type of Manuscript
- PAPER
- Category
- Biocybernetics, Neurocomputing
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Hongge LI, Yoshihiro HAYAKAWA, Shigeo SATO, Koji NAKAJIMA, "Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic" in IEICE TRANSACTIONS on Information,
vol. E89-D, no. 9, pp. 2572-2578, September 2006, doi: 10.1093/ietisy/e89-d.9.2572.
Abstract: In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e89-d.9.2572/_p
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@ARTICLE{e89-d_9_2572,
author={Hongge LI, Yoshihiro HAYAKAWA, Shigeo SATO, Koji NAKAJIMA, },
journal={IEICE TRANSACTIONS on Information},
title={Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic},
year={2006},
volume={E89-D},
number={9},
pages={2572-2578},
abstract={In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.},
keywords={},
doi={10.1093/ietisy/e89-d.9.2572},
ISSN={1745-1361},
month={September},}
Copy
TY - JOUR
TI - Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic
T2 - IEICE TRANSACTIONS on Information
SP - 2572
EP - 2578
AU - Hongge LI
AU - Yoshihiro HAYAKAWA
AU - Shigeo SATO
AU - Koji NAKAJIMA
PY - 2006
DO - 10.1093/ietisy/e89-d.9.2572
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E89-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2006
AB - In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.
ER -
English
