Self-connection can enlarge the memory capacity of an associative memory based on the neural network. However, the basin size of the embedded memory state shrinks. The problem of basin size is related to undesirable stable states which are spurious. If we can destabilize these spurious states, we expect to improve the basin size. The inverse function delayed (ID) model, which includes the Bonhoeffer-van der Pol (BVP) model, has negative resistance in its dynamics. The negative resistance of the ID model can destabilize the equilibrium states on certain regions of the conventional neural network. Therefore, the associative memory based on the ID model, which has self-connection in order to enlarge the memory capacity, has the possibility to improve the basin size of the network. In this paper, we examine the fundamental characteristics of an associative memory based on the ID model by numerical simulation and show the improvement of performance compared with the conventional neural network.

In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.