In order to introduce the burst firing, a nerve-cell dynamic feature, we extend the Inverse function Delayed model (ID model), which is the neuron model with ability to oscillate and has powerful ability on the information processing. This dynamics is discussed for the relation with the functional role of the brain and is characterized by repeated patterns of closely spaced action potentials. It is expected that the additional new characteristics add extra functions to neural networks. Using the relation between the ID model and reduced Hodgkin-Huxley model, we propose the neuron model with ability of burst. The proposed model excelled the ID model in solving the N-Queen problem. Additionally, the prototype chip for the burst ID model is implemented and measured.

We have fabricated a new analog memory for integrated artificial neural networks. Several attempts have been made to develop a linear characteristics of floating-gate analog memorys with feedback circuits. The learning chip has to have a large number of learning control circuit. In this paper, we propose a new analog memory SDAM with three cascaded TFTs. The new analog memory has a simple design, a small area occupancy, a fast switching speed and an accurate linearity. To improve accurate linearity, we propose a new chargetransfer process. The device has a tunnel junction (poly-Si/poly-Si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating-gate MOSFET. The diffusion of the charges injected through the tunnel junction are controlled by a source follower operation of a thin film transistor (TFT). The proposed operation is possible that the amounts of transferred charges are constant independent of the charges in storage capacitor.

In this paper, we describe two approaches to optimize the Phase-Mode pipelined parallel multiplier. One of the approaches is reforming a data distribution for an AND array, which is named the hybrid structure. Another method is applying a Booth encoder as a substitute of the AND array in order to generate partial products. We design a 2-bit 2-bit Phase-Mode Booth encoder and test the circuit by the numerical simulations. The circuit consists of 21 ICF gates and operates correctly at a throughput of 37.0 GHz. The numbers of Josephson junctions and the pipelined stages in each scale of multipliers are reduced remarkably by using the encoder. According to our estimations, the Phase-Mode Booth encoder is the effective component to improve the performance of large-scale parallel multipliers.

Further development of a network based on the Inverse Function Delayed (ID) model which can recall temporal sequences of patterns, is proposed. Additional advantage is taken of the negative resistance region of the ID model and its hysteretic properties by widening the negative resistance region and letting the output of the ID neuron be almost instant. Calling this neuron limit ID neuron, a model with limit ID neurons connected pairwise with conventional neurons enlarges the storage capacity and increases it even further by using a weightmatrix that is calculated to guarantee the storage after transforming the sequence of patterns into a linear separation problem. The network's tolerance, or the model's ability to recall a sequence, starting in a pattern with initial distortion is also investigated and by choosing a suitable value for the output delay of the conventional neuron, the distortion is gradually reduced and finally vanishes.

The utilization of a high-Tc superconductor for implementing a superconducting qubit is to be expected. Recent researches on the quantum property of Josephson junctions in high-Tc superconductors indicate that the low energy quasiparticle excitation is weak enough to observe the macroscopic quantum tunneling. Therefore, a detailed study on the quantum property of high-Tc Josephson junctions becomes more important for applications. We show our experimental results of the macroscopic tunneling of current biased intrinsic Josephson junctions in Bi-2212 and its resonant activation in the presence of microwave radiation.

Majority logic is quite important for various applications such as fault tolerant systems, threshold logic, spectrum spread coding, and artificial neural networks. The circuit implementation of majority logic is difficult when the number of inputs becomes large because the number of transistors becomes huge and serious delay would occur. In this paper, we propose a new majority circuit with large fan-in. The circuit is composed of ordinary CMOS transistors and the total number of transistors is approximately only 4N, where N is the total number of inputs. We confirmed a correct operation by using HSPICE simulation. The yield of the proposed circuit was evaluated with respect to N under the variations of device parameters by using Monte Carlo simulation.

We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.

Single electron devices are ultra low power and extremely small devices, and suitable for implementation of large scale integrated circuits. Artificial neural networks (ANNs), which require a large number of transistors for being to be applied to practical use, is one of the possible applications of single electron devices. In order to simplify a single electron circuit configuration, we apply stochastic logic in which various complex operations can be done with basic logic gates. We design basic subcircuits of a single electron stochastic neural network, and confirm that backgate bias control and a redundant configuration are necessary for a feedback loop configuration by computer simulation based on Monte Carlo method. The proposed single electron circuit is well-suited for hardware implementation of a stochastic neural network because we can save circuit area and power consumption by using a single electron random number generator (RNG) instead of a conventional complementary metal oxide semiconductor (CMOS) RNG.

The hardware implementation of a neural network model using stochastic logic has been able to integrate numerous neuron units on a chip. However, the limitation of applications occurred since the stochastic neurosystem could execute only discrete-time dynamics. We have contrived a neuron model with continuous-time dynamics by using stochastic calculations. In this paper, we propose the circuit design of a new neuron circuit, and show the fabricated neurochip comprising 64 neurons with experimental results. Furthermore, a new asynchronous updating method and a new activation function circuit are proposed. These improvements enhance the performance of the neurochip greatly.

A binary counter circuit in the extended phase-mode logic (EPL) family is presented. The EPL family utilizes a single flux quantum as an information bit carrier. Numerical simulations show that a binary counter circuit with a Josephson critical current density of 1 kA/cm2 can operate up to a 30 GHz input signal. The circuit has been fabricated using Nb/AlOx/Nb Josephson junction technology. New interface circuits are employed in the fabricated chip. A low speed test result shows the correct operation of the binary counter.

A chaotic noise is one of the most important implements for information processing such as neural networks. It has been suggested that chaotic neural networks have high performance ability for information processing. In this paper, we report two designs of a compact chaotic noise generator for large integration circuits using CMOS technology. The chaotic noise is generated using map chaos. We design both of the logistic map type and the tent map type circuits. These chaotic noise generators are compact as compared with the other circuits. The results show that the successful chaotic operations of the circuits because of the positive Lyapunov number. We calculate the Lyapunov exponents to certify the results of the chaotic operations. However, it is hard to estimate its accurate number for noisy data using the conventional method. And hence, we propose the modified calculation of the Lyapunov exponent for noisy data. These two circuits are expected to be utilized for various applications.

A network based on the Inverse Function Delayed (ID) model which can recall a temporal sequence of patterns, is proposed. The classical problem that the network is forced to make long distance jumps due to strong attractors that have to be isolated from each other, is solved by the introduction of the ID neuron. The ID neuron has negative resistance in its dynamics which makes a gradual change from one attractor to another possible. It is then shown that a network structure consisting of paired conventional and ID neurons, perfectly can recall a sequence.

In this paper, a simple method to investigate the dynamics of continuous-time neural networks based on the force (kinetic vector) derived from the equation of motion for neural networks instead of the energy function of the system has been described. The number of equilibrium points and limit cycles of one-dimensional neural networks with the asymmetric cyclic connection matrix has been investigated experimently by this method. Some types of equilibrium points and limit cycles have been theoretically analyzed. The relations between the properties of limit cycles and the number of connections also have been discussed.

We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural system. We use a 4-bit SRAM as the memory for synaptic weights. The expected I/O characteristics of the neurons and the synapses were measured experimentally. We have also demonstrated the capability of network operation with the use of synaptic weights, for solving the A/D conversion problem.

Self-connection can enlarge the memory capacity of an associative memory based on the neural network. However, the basin size of the embedded memory state shrinks. The problem of basin size is related to undesirable stable states which are spurious. If we can destabilize these spurious states, we expect to improve the basin size. The inverse function delayed (ID) model, which includes the Bonhoeffer-van der Pol (BVP) model, has negative resistance in its dynamics. The negative resistance of the ID model can destabilize the equilibrium states on certain regions of the conventional neural network. Therefore, the associative memory based on the ID model, which has self-connection in order to enlarge the memory capacity, has the possibility to improve the basin size of the network. In this paper, we examine the fundamental characteristics of an associative memory based on the ID model by numerical simulation and show the improvement of performance compared with the conventional neural network.

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called "switched diffusion analog memory with feedback circuit (FBSDAM). " FBSDAM has linear writing and erasing characteristics. Therefore, FBSDAM is useful for memorizing an analog value exactly. We also propose a new analog content-addressable memory (CAM) which has neural-like learning and discriminating functions which discriminate whether an incoming pattern is an unknown pattern or a stored pattern. We design and fabricate the CAM using FBSDAM by means of the 4µm double-poly single-metal CMOS process and nonvolatile analog memory technology which are developed by us. The chip size is 3.1 mm3.1 mm. We estimate that the CAM is composed of 50 times fewer transistors and requires 70 times fewer calculation steps than a typical digital computer implemented using similar technology.

The threshold characteristics of mutually coupled SQUIDs (Superconducting Quantum Interference Devices) have been analytically and numerically investigated. The mutually coupled SQUIDs investigated is composed of an rf-SQUID and a dc-SQUID. Here, the rf-SQUID is a flux quantum generator and the dc-SQUID is a flux detector. The linearization method substituting sin-1x by (π/2)x (1x1) is found valid when it is applied to the mutually coupled SQUIDs, because it is possible to obtain the superconducting regions analytically. By computer implementation of linearization method, we found this method is very effective and very quick compared to the ordinary methods. We report the internal flux on an rf-SQUID, the threshold of a dc-SQUID, and that of mutually coupled SQUIDs obtained by Lagrange multiplier formulation and linearization. The features of the threshold characteristics of the mutually coupled SQUIDs with various parameters are also reported. The discontinuous behavior of threshold of the mutually coupled SQUIDs are attractive for digital applications. We suggest three applications of the mutually coupled SQUIDs, that is, a logic gate for high-Tc superconductors (HTSs), a neuron device, and an A/D converter.

We have fabricated a new analog memory with a floating gate as a key component to store synaptic weights for integrated artificial neural networks. The new analog memory comprises a tunnel junction (poly-Si/poly-si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating gate MOSFET. The diffusion of the charges injected through the tunnel junction is controlled by switching operation of the thin-film transistor, and we refer to the new analog memory as switched diffusion analog memory (SDAM). The obtained characteristics of SDAM are a fast switching speed and an improved linearity between the potential of the floating gate and the number of pulse inputs. SDAM can be used in a neural network in which write/erase and read operations are performed simultaneously.

Many researchers have attempted to solve the combinatorial optimization problems, that are NP-hard or NP-complete problems, by using neural networks. Though the method used in a neural network has some advantages, the local minimum problem is not solved yet. It has been shown that the Inverse Function Delayed (ID) model, which is a neuron model with a negative resistance on its dynamics and can destabilize an intended region, can be used as the powerful tool to avoid the local minima. In our previous paper, we have shown that the ID network can separate local minimum states from global minimum states in case that the energy function of the embed problem is zero. It can achieve 100% success rate in the N-Queen problem with the certain parameter region. However, for a wider parameter region, the ID network cannot reach a global minimum state while all of local minimum states are unstable. In this paper, we show that the ID network falls into a particular permanent oscillating state in this situation. Several neurons in the network keep spiking in the particular permanent oscillating state, and hence the state transition never proceed for global minima. However, we can also clarify that the oscillating state is controlled by the parameter α which affects the negative resistance region and the hysteresis property of the ID model. In consequence, there is a parameter region where combinatorial optimization problems are solved at the 100% success rate.