In this paper, a simple method to investigate the dynamics of continuous-time neural networks based on the force (kinetic vector) derived from the equation of motion for neural networks instead of the energy function of the system has been described. The number of equilibrium points and limit cycles of one-dimensional neural networks with the asymmetric cyclic connection matrix has been investigated experimently by this method. Some types of equilibrium points and limit cycles have been theoretically analyzed. The relations between the properties of limit cycles and the number of connections also have been discussed.

In this paper, we propose the majority algorithm to choose the connection weights for the neural networks with quantized connection weights of 1 and 0. We also obtained the layered network to solve the parity problem with the input of arbitrary number N through an application of this algorithm. The network can be expected to have the same ability of generalization as the network trained with learning rules. This is because it is possible to decide the connection weights, regardless of the size of the training set. One can decide connection weights without learning according to our case study. Thus, we expect that the proposed algorithm may be applied for a real-time processing.

Evaluation of cyclic transitions in the discrete-time neural networks with antisymmetric and circular interconnection weights has been derived in an asymptotic mathematical form. The type and the number of limit cycles generated by circular networks, in which each neuron is connected only to its nearest neurons, have been investigated through analytical method. The results show that the estimated numbers of state vectors generating n- or 2n-periodic limit cycles are an exponential function of (1.6)n for a large number of neuron, n. The sufficient conditions for state vectors to generate limit cycles of period n or 2n are also given.

In order to investigate the dynamic behavior of quantized interconnection neural networks on neuro-chips, we have designed and fabricated hardware neural networks according to design rule of a 1.2 µm CMOS technology. To this end, we have developed programmable synaptic weights for the interconnection with three values of 1 and 0. We have tested the chip and verified the dynamic behavior of the networks in a circuit level. As a result of our study, we can provide the most straightforward application of networks for a dynamic pattern classifier. The proposed network is advantageous in that it does not need extra exemplar to classify shifted or reversed patterns.