LSI Neural Chip of Pulse-Output Network with Programmable Synapse

Shigeo SATO; Manabu YUMINE; Takayuki YAMA; Junichi MUROTA; Koji NAKAJIMA; Yasuji SAWADA

LSI Neural Chip of Pulse-Output Network with Programmable Synapse

Shigeo SATO, Manabu YUMINE, Takayuki YAMA, Junichi MUROTA, Koji NAKAJIMA, Yasuji SAWADA

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We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural system. We use a 4-bit SRAM as the memory for synaptic weights. The expected I/O characteristics of the neurons and the synapses were measured experimentally. We have also demonstrated the capability of network operation with the use of synaptic weights, for solving the A/D conversion problem.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.1 pp.94-100

Publication Date: 1995/01/25

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Shigeo SATO, Manabu YUMINE, Takayuki YAMA, Junichi MUROTA, Koji NAKAJIMA, Yasuji SAWADA, "LSI Neural Chip of Pulse-Output Network with Programmable Synapse" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 1, pp. 94-100, January 1995, doi: .
Abstract: We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural system. We use a 4-bit SRAM as the memory for synaptic weights. The expected I/O characteristics of the neurons and the synapses were measured experimentally. We have also demonstrated the capability of network operation with the use of synaptic weights, for solving the A/D conversion problem.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_1_94/_p

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@ARTICLE{e78-c_1_94,
author={Shigeo SATO, Manabu YUMINE, Takayuki YAMA, Junichi MUROTA, Koji NAKAJIMA, Yasuji SAWADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={LSI Neural Chip of Pulse-Output Network with Programmable Synapse},
year={1995},
volume={E78-C},
number={1},
pages={94-100},
abstract={We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural system. We use a 4-bit SRAM as the memory for synaptic weights. The expected I/O characteristics of the neurons and the synapses were measured experimentally. We have also demonstrated the capability of network operation with the use of synaptic weights, for solving the A/D conversion problem.},
keywords={},
doi={},
ISSN={},
month={January},}

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TY - JOUR
TI - LSI Neural Chip of Pulse-Output Network with Programmable Synapse
T2 - IEICE TRANSACTIONS on Electronics
SP - 94
EP - 100
AU - Shigeo SATO
AU - Manabu YUMINE
AU - Takayuki YAMA
AU - Junichi MUROTA
AU - Koji NAKAJIMA
AU - Yasuji SAWADA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 1995
AB - We have fabricated a microchip of a neural circuit with pulse representation. The neuron output is a voltage pulse train. The synapse is a constant current source whose output is proportional to the duty ratio of neuron output. Membrane potential is charged by collection of synaptic currents through a RC circuit, providing an analog operation similar to the biological neural system. We use a 4-bit SRAM as the memory for synaptic weights. The expected I/O characteristics of the neurons and the synapses were measured experimentally. We have also demonstrated the capability of network operation with the use of synaptic weights, for solving the A/D conversion problem.
ER -