Recent years have seen a general resurgence of interest in analog signal processing and computing architectures. In addition, extensive theoretical and experimental literature on chaos and analog chaotic oscillators exists. One peculiarity of these circuits is the ability to generate, despite their structural simplicity, complex spatiotemporal patterns when several of them are brought towards synchronization via coupling mechanisms. While by no means a systematic survey, this paper provides a personal perspective on this area. After briefly covering design aspects and the synchronization phenomena that can arise, a selection of results exemplifying potential applications is presented, including in robot control, distributed sensing, reservoir computing, and data augmentation. Despite their interesting properties, the industrial applications of these circuits remain largely to be realized, seemingly due to a variety of technical and organizational factors including a paucity of design and optimization techniques. Some reflections are given regarding this situation, the potential relevance to discontinuous innovation in analog circuit design of chaotic oscillators taken both individually and as synchronized networks, and the factors holding back the transition to higher levels of technology readiness.

This paper proposes a novel differential active self-interference canceller (DASIC) algorithm for asynchronous in-band full-duplex (IBFD) Gaussian filtered frequency shift keying (GFSK), which is designed for wireless Internet of Things (IoT). In IBFD communications, where two terminals simultaneously transmit and receive signals in the same frequency band, there is an extremely strong self-interference (SI). The SI can be mitigated by an active SI canceller (ASIC), which subtracts an interference replica based on channel state information (CSI) from the received signal. The challenging problem is the realization of asynchronous IBFD for wireless IoT in indoor environments. In the asynchronous mode, pilot contamination is induced by the non-orthogonality between asynchronous pilot sequences. In addition, the transceiver suffers from analog front-end (AFE) impairments, such as phase noise. Due to these impairments, the SI cannot be canceled entirely at the receiver, resulting in residual interference. To address the above issue, the DASIC incorporates the principle of the differential codec, which enables to suppress SI without the CSI estimation of SI owing to the differential structure. Also, on the premise of using an error correction technique, iterative detection and decoding (IDD) is applied to improve the detection capability while exchanging the extrinsic log-likelihood ratio (LLR) between the maximum a-posteriori probability (MAP) detector and the channel decoder. Finally, the validity of using the DASIC algorithm is evaluated by computer simulations in terms of the packet error rate (PER). The results clearly demonstrate the possibility of realizing asynchronous IBFD.

This article reviews the author’s group research achievements in analog/mixed-signal circuit and system area with introduction of how they came up with the ideas. Analog/mixed-signal circuits and systems have to be designed as well-balanced in many aspects, and coming up ideas needs some experiences and discussions with researchers. It is also heavily dependent on researchers. Here, the author’s group own experiences are presented as well as their research motivations.

In a field of biomedical engineering, not only low-pass filters for high frequency elimination but also notch filters for suppressing powerline interference are necessary to process low-frequency biosignals. For integration of low-frequency filters, chip implementation of large capacitances is major difficulty. As methods to enhance capacitances with small chip area, use of capacitance multipliers is effective. This letter describes design consideration of integrated low-frequency low-pass notch filter employing capacitance multipliers. Two main points are presented. Firstly, a new floating capacitance multiplier is proposed. Secondly, a technique to reduce the number of capacitance multipliers is proposed. By this technique, power consumption is reduced. The proposed techniques are applied a 3rd order low-pass notch filter. Simulation results show the effectiveness of the proposed techniques.

In this paper, a circuit based on a field programmable analog array (FPAA) is proposed for three types of chaotic spiking oscillator (CSO). The input/output conversion characteristics of a specific element in the FPAA can be defined by the user. By selecting the proper characteristics, three types of CSO are realized without changing the structure of the circuit itself. Chaotic attractors are observed in a hardware experiment. It is confirmed that the dynamics of the CSOs are consistent with numerical simulations.

In 5th generation (5G) and Beyond 5G mobile communication systems, it is expected that numerous antennas will be densely deployed to realize ultra-broadband communication and uniform coverage. However, as the number of antennas increases, total power consumption of all antennas will also increase, which leads to a negative impact on the environment and operating costs of telecommunication operators. Thus, it is necessary to simplify an antenna structure to suppress the power consumption of each antenna. On the other hand, as a way to realize ultra-broadband communication, millimeter waves will be utilized because they can transmit signals with a broader bandwidth than lower frequencies. However, since millimeter waves have a large propagation loss, a propagation distance is shorter than that of low frequencies. Therefore, in order to extend the propagation distance, it is necessary to increase an equivalent isotropic radiated power by beamforming with phased array antenna. In this paper, a phased antenna array module in combined with analog radio over fiber (A-RoF) technology for 40-GHz millimeter wave is developed and evaluated for the first time. An 8×8 phased array antenna for 40-GHz millimeter wave with integrated photodiodes and RF chains has been developed, and end-to-end transmission experiment including 20km A-RoF transmission and 3-m over-the-air transmission from the developed phased array antenna has been conducted. The results showed that the 40-GHz RF signal after the end-to-end transmission satisfied the criteria of 3GPP signal quality requirements within ±50 degrees of main beam direction.

Recent years have seen a decline in the art of analog IC design even though analog interface and analog signal processing remain just as essential as ever. While there are many contributing factors, four specific pressures which contribute the most to the loss of creativity and innovation within analog practice are examined: process evolution, risk aversion, digitally assisted analog, and corporate culture. Despite the potency of these forces, none are found to be insurmountable obstacles to reinvigorating the industry. A more creative future is within our reach.

In this research, we investigated the threshold voltage (VTH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2Pr) of 7.2 μC/cm2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the VTH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.

This paper presents a novel frequency-controlled beam steering scheme for a phased-array antenna system (PAS). The proposed scheme employs phase-controlled carrier signals to form the PAS beam. Two local oscillators (LOs) and delay lines are used to generate the carrier signals. The carrier of one LO is divided into branches, and then the divided carriers passing through the corresponding delay lines have the desired phase relationship, which depends on the oscillation frequency of the LO. To confirm the feasibility of the scheme, four-branch PAS transmitters are configured and tested in a 10-GHz frequency band. The results verify that the formed beam is successfully steered in a wide range, i.e., the 3-dB beamwidth of approximately 100 degrees, using LO frequency control.

A multibeam massive multiple input multiple output (MIMO) configuration employs beam selection with high power in the analog part and executes a blind algorithm such as the independent component analysis (ICA), which does not require channel state information in the digital part. Two-dimensional (2-D) multibeams are considered in actual power losses and beam steering errors regarding the multibeam patterns. However, the performance of these 2-D beams depends on the beam pattern of the multibeams, and they are not optimal multibeam patterns suitable for multibeam massive MIMO configurations. In this study, we clarify the performance difference due to the difference of the multibeam pattern and consider the multibeam pattern suitable for the system condition. Specifically, the optimal multibeam pattern was determined with the element spacing and beamwidth of the element directivity as parameters, and the effectiveness of the proposed method was verified via computer simulations.

This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.

In March 2020, the 5th generation mobile communication system (5G) was launched in Japan. Frequency bands of 3.7GHz, 4.5GHz and 28GHz were allocated for 5G services, and the 5G use cases fall into three broad categories: Enhanced Mobile Broadband (eMBB), Massive Machine Type Communication (mMTC) and Ultra-Reliable Low Latency Communication (URLLC). The use cases and services that take advantage of the characteristics of each category are expected to be put to practical use, and experiments of practical use are underway. This paper introduces and demonstrates a touchless gate that can identify, authenticate and allow passage through the gate by using these features and 5G beam tracking to estimate location by taking advantage of the low latency of 5G and the straightness of the 28GHz band radio wave and its resistance to spreading. Since position estimation error due to reflected waves and other factors has been a problem, we implement an algorithm that tracks the beam and estimates the user's line of movement, and by using an infrared sensor, we made it possible to identify the gate through which the user passes with high probability. We confirmed that the 5G touchless gate is feasible for gate passage. In addition, we demonstrate that a new service based on high-speed high-capacity communication is possible at gate passage by taking advantage of the wide bandwidth of the 28GHz band. Furthermore, as a use case study of the 5G touchless gate, we conducted a joint experiment with an airline company.

In this paper, we focus on developing efficient multi-configuration selection mechanisms by exploiting the spatial degrees of freedom (DoF), and leveraging the simple design benefits of spatial modulation (SM). Notably, the SM technique, as well as its variants, faces the following critical challenges: (i) the performance degradation and difficulty in improving the system performance for higher-level QAM constellations, and (ii) the vast complexity cost in precoder designs particularly for the increasing system dimension and amplitude-phase modulation (APM) constellation dimension. Given this situation, we first investigate two independent modulation domains, i.e., the original signal- and spatial-constellations. By exploiting the analog shift weighting and the virtual spatial signature technologies, we introduce the signature spatial modulation (SSM) concept, which is capable of guaranteing superior trade-offs among spectral- and cost-efficiencies, and system bit error rate (BER) performance. Besides, we develop an analog beamforming for SSM by solving the introduced unconstrained Lagrange dual function minimization problem. Numerical results manifest the performance gain brought by our developed analog beamforming for SSM.

The hybrid precoding (HP) technique has been widely considered as a promising approach for millimeter wave communication systems. In general, the existing HP structure with a complicated high-resolution phase shifter network can achieve near-optimal spectral efficiency, however, it involves high energy consumption. The HP architecture with an energy-efficient switch network can significantly reduce the energy consumption. To achieve maximum energy efficiency, this paper focuses on the HP architecture with switch network and considers a novel adaptive analog network HP structure for such mmWave MIMO systems, which can provide potential array gains. Moreover, a multiuser adaptive coordinate update algorithm is proposed for the HP design problem of this new structure. Simulation results verify that our proposed design can achieve better energy efficiency than other recently proposed HP schemes when the number of users is small.

C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This paper proposes an algorithm calibrating the non-linearity by γ-estimation to accurately estimate radix greater than 2 required to realize C-C SAR-ADC. Behavioral analyses show that the radix γ-estimation error become within 1.5, 0.4 and 0.1% in case of 8-, 10- and 12-bit resolution ADC, respectively. SPICE simulations show that the γ-estimation satisfies the requirement of 10-bit resolution C-C SAR-ADC. The C-C SAR-ADC using γ-estimation achieves 9.72bit of ENOB, 0.8/-0.5LSB and 0.5/-0.4LSB of DNL/INL.

Impact of sampling frequency and the number of quantization bit of analog-to-digital conversion (ADC) in a direct detection lightwave system using Kramers-Kronig (KK) relation, which has been attracting attention in recent years, are numerically investigated. We studied the effect of spectral broadening caused by nonlinear operations (logarithm, square root) of the KK algorithm when the frequency gap (shift frequency) between the modulated signal and the optical tone is varied. We found that reception performances depend on both the ADC bandwidth and the relative positions of the optical tone and the spectrum. Spectral broadening caused by the logarithm operation of the KK algorithm is found to be the dominant factor of signal distortion in an ADC bandwidth limited system. We studied the effect of the number of quantization bit on the error vector magnitude (EVM) of KK relation based reception in a carrier-to-signal power ratio (CSPR) adjustable transmission system. We found that performances of KK relation based receiver can be improved by increasing the number of quantization bits. For minimum-phase-condition satisfied KK receiver, the required number of quantization bit was found to be 5 bits or more for detection of QPSK, 16-QAM and 64-QAM-modulated signal after 20-km transmission.

A high degree of freedom in spectral domain allows us to accommodate additional optical signal processing for wavelength division multiplexing in photonic analog-to-digital conversion. We experimentally verified a spectral compression to save a necessary bandwidth for soliton self-frequency shift based optical quantization through the cascade of the four-wave mixing based and the sum-frequency generation based spectral compression. This approach can realize 0.03 nm individual bandwidth correspond to save up to more than 85 percent of bandwidth for 7-bit optical quantization in C-band.

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.

A programmable analog calculation unit (ACU) is designed for vector computations in continuous-time with compact circuit scale. From our early study, it is feasible to retrieve arbitrary two-variable functions through support vector regression (SVR) in silicon. In this work, the dimensions of regression are expanded for vector computations. However, the hardware cost and computing error greatly increase along with the expansion of dimensions. A two-stage architecture is proposed to organize multiple ACUs for high dimensional regression. The computation of high dimensional vectors is separated into several computations of lower dimensional vectors, which are implemented by the free combination of several ACUs with lower cost. In this manner, the circuit scale and regression error are reduced. The proof-of-concept ACU is designed and simulated in a 0.18μm technology. From the circuit simulation results, all the demonstrated calculations with nine operands are executed without iterative clock cycles by 4960 transistors. The calculation error of example functions is below 8.7%.

Ring voltage-controlled-oscillators (VCOs) are increasingly being used to design ΔΣ ADCs. They have the merits of simple, highly digital and low-voltage tolerant, making them attractive alternatives for the classic scaling-unfriendly operational-amplifier-based methodology. This paper aims to provide a summary on the advancement of VCO-based ΔΣ ADCs. The scope of this paper includes the basics and motivations behind the VCO-based ADCs, followed by a survey covering a wide range of architectures and circuit techniques in both continuous-time (CT) and discrete-time (DT) implementation, and will discuss the key insights behind the contributions and drawbacks of these architectures.