IEICE TRANSACTIONS on Fundamentals
Density Optimization for Analog Layout Based on Transistor-Array
Summary :
In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.12 pp.1720-1730
- Publication Date
- 2019/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E102.A.1720
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Chao GENG
The University of Kitakyushu
Bo LIU
Henan University of Science and Technology
Shigetoshi NAKATAKE
The University of Kitakyushu
Keyword
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Chao GENG, Bo LIU, Shigetoshi NAKATAKE, "Density Optimization for Analog Layout Based on Transistor-Array" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 12, pp. 1720-1730, December 2019, doi: 10.1587/transfun.E102.A.1720.
Abstract: In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.1720/_p
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@ARTICLE{e102-a_12_1720,
author={Chao GENG, Bo LIU, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Density Optimization for Analog Layout Based on Transistor-Array},
year={2019},
volume={E102-A},
number={12},
pages={1720-1730},
abstract={In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.},
keywords={},
doi={10.1587/transfun.E102.A.1720},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Density Optimization for Analog Layout Based on Transistor-Array
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1720
EP - 1730
AU - Chao GENG
AU - Bo LIU
AU - Shigetoshi NAKATAKE
PY - 2019
DO - 10.1587/transfun.E102.A.1720
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2019
AB - In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.
ER -
English
