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Density Optimization for Analog Layout Based on Transistor-Array

Chao GENG, Bo LIU, Shigetoshi NAKATAKE

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Summary :

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.12 pp.1720-1730
Publication Date
2019/12/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E102.A.1720
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category

Authors

Chao GENG
  The University of Kitakyushu
Bo LIU
  Henan University of Science and Technology
Shigetoshi NAKATAKE
  The University of Kitakyushu

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