In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile it shows a good circuit performance in the post-layout simulation.

This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of an input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC-offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.

The shape-based routing needs a routing architecture with a geometrical computation framework on it. This paper introduces a novel routing architecture, Oct-Touched Tile (OTT), with a geometrical computation method along the horizontal- and vertical-constraints. The architecture is represented by the tiles spreading over the 2-D plane. Each tile is flexible to satisfy the constraints imposed for non-overlapping and sizing request. In this framework, path finding and shape-based sizing are executed on the same architecture. In experiments, our system demonstrates the performance comparable to a commercial tool. In addition, we show potential of OTT by introducing several ideas of extensions to analog layout constraints.

An analog standard cell layout configuration is proposed for simplifying the design and reducing the man-hours for designing mixed analog-digital LSIs, and analog standard cells are fabricated for A-D and D-A converters with Δ-Σ modulators. This works seeks to implement 2-D cell placement with up-down and left-right mirror rotation and shorter high-impedance analog wiring than conventional 1-D placement in order to obtain high-performance analog characteristics. By considering sensitivity to noise, routing channels have been classified into 4 types: high-impedance analog, low-impedance analog, analog-digital, and digital, and efforts have been made to prevent analog wires from crossing over digital wires. In addition to power and analog ground wires, analog standard cells have built-in analog ground wires with attached wells optimized for shielding. These wires are interconnected to a new isolation cell that separates analog circuits from digital circuits and routing channels. Based on the above layout structure, 46 different types of analog standard cells have been designed. Also, the analog part of Δ-Σ type A-D and D-A converters can be automatically designed in conjunction with interactive processing and chips fabricated by using these cells. It was found that, compared to manual design, one could easily obtain a chip occupying less than 1.5-times the area with about 2/3 the man-days using this approach. In comparison with manual design, it was also found that the S/N ratio could be reduced from about 6 to 7 dB.

We propose a new compaction problem that allows layout elements to have many shape possibilities. The objective of the problem is to find not only positions but also shapes of layout elements. We present an efficient method to solve the problem--compaction with shape optimization. This method simplifies the problem by considering the optimization of shapes only for the layout elements on a critical path. The layout is compacted step by step while optimizing the shapes of layout elements. Another importance of this compaction technique is that it makes layout to be "recyclable" for other set of device parameters. The experimental examples, which attempt shape optimization and recycle of analog layout, confirms the importance and efficiency of our method.

An automatic macrocell generator has been developed and applied to the analog layout of SC and active-RC filters. The generator consists of a process independent generation procedure, a leafcell library, and a circuit description of the leafcells. The unit element arrays of the whole filter are generated together to minimize the array height of the entire filter macrocell, so that the area of the generated filter is as small as that of a manually laid out filter. Three SC filters and one active-RC filter were designed and fabricated by 1.5-µm CMOS technology, that successfully yielded an S/N ratio of more than 70 dB with a quick turn around time.

A layout system for mixed analog/digital standard cell LSI's is described. The system includes interactive floorplan and placement features and automatic global and channel router. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in areas that are free of digital nets as much as possible. The number of line crossovers, especially for analog nets, is minimized by both global and detailed routers, because these crossovers are the dominant factors in the crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. Experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.