IEICE TRANSACTIONS on Electronics
A Layout System for Mixed A/D Standard Cell LSI's
Summary :
A layout system for mixed analog/digital standard cell LSI's is described. The system includes interactive floorplan and placement features and automatic global and channel router. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in areas that are free of digital nets as much as possible. The number of line crossovers, especially for analog nets, is minimized by both global and detailed routers, because these crossovers are the dominant factors in the crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. Experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.3 pp.322-332
- Publication Date
- 1992/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Analog LSI and Related Technology)
- Category
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Ikuo HARADA, Hitoshi KITAZAWA, Takao KANEKO, "A Layout System for Mixed A/D Standard Cell LSI's" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 3, pp. 322-332, March 1992, doi: .
Abstract: A layout system for mixed analog/digital standard cell LSI's is described. The system includes interactive floorplan and placement features and automatic global and channel router. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in areas that are free of digital nets as much as possible. The number of line crossovers, especially for analog nets, is minimized by both global and detailed routers, because these crossovers are the dominant factors in the crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. Experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_3_322/_p
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@ARTICLE{e75-c_3_322,
author={Ikuo HARADA, Hitoshi KITAZAWA, Takao KANEKO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Layout System for Mixed A/D Standard Cell LSI's},
year={1992},
volume={E75-C},
number={3},
pages={322-332},
abstract={A layout system for mixed analog/digital standard cell LSI's is described. The system includes interactive floorplan and placement features and automatic global and channel router. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in areas that are free of digital nets as much as possible. The number of line crossovers, especially for analog nets, is minimized by both global and detailed routers, because these crossovers are the dominant factors in the crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. Experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - A Layout System for Mixed A/D Standard Cell LSI's
T2 - IEICE TRANSACTIONS on Electronics
SP - 322
EP - 332
AU - Ikuo HARADA
AU - Hitoshi KITAZAWA
AU - Takao KANEKO
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1992
AB - A layout system for mixed analog/digital standard cell LSI's is described. The system includes interactive floorplan and placement features and automatic global and channel router. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in areas that are free of digital nets as much as possible. The number of line crossovers, especially for analog nets, is minimized by both global and detailed routers, because these crossovers are the dominant factors in the crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. Experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.
ER -
English
