IEICE TRANSACTIONS on Fundamentals
Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation
Summary :
This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of an input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC-offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.7 pp.1381-1389
- Publication Date
- 2016/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.1381
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Takuya HIRATA
the University of Kitakyushu
Ryuta NISHINO
the University of Kitakyushu
Shigetoshi NAKATAKE
the University of Kitakyushu
Masaya SHIMOYAMA
the University of Miyazaki
Masashi MIYAGAWA
the University of Miyazaki
Ryoichi MIYAUCHI
the University of Miyazaki
Koichi TANNO
the University of Miyazaki
Akihiro YAMADA
the A. LSI. Design Co., LTD, Japan
Keyword
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Takuya HIRATA, Ryuta NISHINO, Shigetoshi NAKATAKE, Masaya SHIMOYAMA, Masashi MIYAGAWA, Ryoichi MIYAUCHI, Koichi TANNO, Akihiro YAMADA, "Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 7, pp. 1381-1389, July 2016, doi: 10.1587/transfun.E99.A.1381.
Abstract: This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of an input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC-offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.1381/_p
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@ARTICLE{e99-a_7_1381,
author={Takuya HIRATA, Ryuta NISHINO, Shigetoshi NAKATAKE, Masaya SHIMOYAMA, Masashi MIYAGAWA, Ryoichi MIYAUCHI, Koichi TANNO, Akihiro YAMADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation},
year={2016},
volume={E99-A},
number={7},
pages={1381-1389},
abstract={This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of an input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC-offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.},
keywords={},
doi={10.1587/transfun.E99.A.1381},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1381
EP - 1389
AU - Takuya HIRATA
AU - Ryuta NISHINO
AU - Shigetoshi NAKATAKE
AU - Masaya SHIMOYAMA
AU - Masashi MIYAGAWA
AU - Ryoichi MIYAUCHI
AU - Koichi TANNO
AU - Akihiro YAMADA
PY - 2016
DO - 10.1587/transfun.E99.A.1381
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2016
AB - This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of an input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC-offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.
ER -
English
