The search functionality is under construction.
The search functionality is under construction.

Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation

Takuya HIRATA, Ryuta NISHINO, Shigetoshi NAKATAKE, Masaya SHIMOYAMA, Masashi MIYAGAWA, Ryoichi MIYAUCHI, Koichi TANNO, Akihiro YAMADA

  • Full Text Views

    0

  • Cite this

Summary :

This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of an input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC-offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.7 pp.1381-1389
Publication Date
2016/07/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E99.A.1381
Type of Manuscript
Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category

Authors

Takuya HIRATA
  the University of Kitakyushu
Ryuta NISHINO
  the University of Kitakyushu
Shigetoshi NAKATAKE
  the University of Kitakyushu
Masaya SHIMOYAMA
  the University of Miyazaki
Masashi MIYAGAWA
  the University of Miyazaki
Ryoichi MIYAUCHI
  the University of Miyazaki
Koichi TANNO
  the University of Miyazaki
Akihiro YAMADA
  the A. LSI. Design Co., LTD, Japan

Keyword