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[Author] Tomoyasu KITAURA(2hit)

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  • A Precise Event-Driven MOS Circhit Simulator

    Tetsuro KAGE  Hisanori FUJISAWA  Fumiyo KAWAFUJI  Tomoyasu KITAURA  

     
    PAPER

      Vol:
    E79-A No:3
      Page(s):
    339-346

    Circuit simulators are used to verify circuit functionality and to obtain detailed timing information before the expensive fabrication process takes place. They have become an essential CAD tool in an era of sub-micron technology. We have developed a new event-driven MOS circuit simulator to replace a direct method circuit simulator. In our simulator, partitioned subcircuits are analyzed by a direct method matrix solver, and these are controlled by an event-driven scheme to maintain accuracy. The key of this approach is how to manage events for circuit simulation. We introduced two types of events: self-control events for a subcircuit and prediction correcting events between subcircuits. They control simulation accuracy, and bring simulation efficiency through multi-rate behavior of a large scale circuit. The event-driven scheme also brings some useful functions which are not available from a direct method circuit simulator, such as a selected block simulation function and a batch simulation function for load variation. We simulated logic modules (buffer, adder, and counter) with about 1000 MOSFETs with our event-driven MOS circuit simulator. Our simulator was 5-7 times faster than a SPICE-like circuit simulator, while maintaining the less than 1% error accuracy. The selected block simulation function enables to shorten simulation time without losing any accuracy by selecting valid blocks in a circuit to simulate specified node waveforms. Using this function, the logic modules were simulated 13-28 times faster than the SPICE-like circuit simulator while maintaining the same accuracy.

  • Hardware Implementation of New Analog Memory for Neural Networks

    Koji NAKAJIMA  Shigeo SATO  Tomoyasu KITAURA  Junichi MUROTA  Yasuji SAWADA  

     
    PAPER-Integrated Electronics

      Vol:
    E78-C No:1
      Page(s):
    101-105

    We have fabricated a new analog memory with a floating gate as a key component to store synaptic weights for integrated artificial neural networks. The new analog memory comprises a tunnel junction (poly-Si/poly-si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating gate MOSFET. The diffusion of the charges injected through the tunnel junction is controlled by switching operation of the thin-film transistor, and we refer to the new analog memory as switched diffusion analog memory (SDAM). The obtained characteristics of SDAM are a fast switching speed and an improved linearity between the potential of the floating gate and the number of pulse inputs. SDAM can be used in a neural network in which write/erase and read operations are performed simultaneously.