A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system.

Using a CCD/CMOS technology, a fully parallel 4 4 focal plane processor, which performs image acquisition, smoothing, and segmentation, had been fabricated and characterized. In this chip, image brightness is converted into signal charge using CCD imaging techniques. The Gaussian smoothing operation is approximated by the repeated application of a simple nearest neighbor binomial convolution mask, realizing the first known use of a true two-dimensional charge division and transfer process. The design allows full control of the spatial extent of the smoothing operation, and incorporates segmentation circuits with global variable threshold control at each pixel location to preserve edges in the image. The processed image is read out using a standard CCD clocking scheme.

This paper describes a radial open stub and its application to a simple design of a four-element planar Butler matrix. In the first stage of our work, we propose a 45-degree phase shifter composed of an eighth-wavelength delay line and a serial connection of a quarter-wavelength straight line and a quarter-wavelength straight open stub. Next, in order to improve relative-phase characteristics between output ports, we propose a 45-degree phase shifter configuration using a quarter-wavelength radial open stub instead of using a quarter-wavelength straight open stub. It is shown by simulation that relative-phase characteristics of the configuration using the radial open stub are better than that using the straight open stub at the high frequencies. Finally, an experimental UHF-band four-element planar Butler matrix is presented. Over the frequency range from 0.83 to 0.92 GHz, the experimental four-element planar Butler matrix exhibits power splits of -6.510.29 dB, return losses of greater than 13 dB, errors in the desired relative-phase difference between output ports of less than 2 degrees.

This paper describes a simple design of a broad-band four-way power divider with 45-degree phase differences between output ports. In the first stage of our work, we present a new broad-band 90-degree power divider. The phase error of the power divider here is less than one-tenth of the conventional 90-degree branch-line hybrid. Next, an experimental UHF-band four-way power divider using a broad-band 90-degree power divider and two broad-band 45-degree power dividers is presented. Over the frequency range from 0.86 to 1.06 GHz, the experimental four-way power divider exhibits power splits of -6.420.25 dB, return losses of greater than 15 dB, errors in the desired relative-phase difference between output ports of less than 1 degree, and isolation between output ports of greater than 15 dB. This divider is useful for realizing low distortion and high efficiency amplifiers without the need for an isolator.

A two-terminal nonlinear element called a resistive fuse is described. Its application in image smoothing and segmentation is explained. Two types CMOS resistive fuses were designed, fabricated, and tested. The first implementation employs four depletion-mode NMOS and PMOS transistors, occupying a minimum area of 30 µm 38 µm. The second implementation uses 7 or 11 standard enhancement-mode transistors on an area of 75 µm 100 µm or less. Individual resistive-fuse circuits have been fabricated and tested and their functionality has been demonstrated. A one-dimensional network of 35 resistive fuses using the 11-transistor implementation was also fabricated in a standard CMOS process. Experimental results indicated that the network is capable of smoothing out small variations in image intensity while preserving the edges of objects.