A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system.