The Quasi-Delay-Insensitive (QDI) model assumes that all the forks are isochronic. The isochronic-fork assumption requires uniform wire delays and uniform switching thresholds of the gates associated with the forking branches. This paper presents a method for determining such forks that do not have to satisfy the isochronic fork requirements, and presents experimental results that show many isochronic forks assumed for existing QDI circuits do not actually have to be "isochronic" or can be even ignored.

This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 µm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

A high efficient HBT MMIC power amplifier with a new on-chip bias control circuit was proposed for PCS applications. By adjusting the quiescent current in accordance with the output power levels, the average power usage efficiency of the power amplifier is improved by a factor of 1.4. The bias controlled power amplifier, depending on low (high) output power levels, shows 62(103) mA of quiescent current, 16(28) dBm output power with 7.5(35.4)% of power-added efficiency(PAE), -46(-45) dBc of adjacent-channel power ratio (ACPR), and 23.7(26.9) dB of gain

An accurate, fast delay calculation method suitable for high-performance, low-power LSI design is proposed. The delay calculation is composed of two steps: (1) the gate delay is calculated by using an effective capacitance obtained from a simple model we propose; and (2) the interconnect delay is also calculated from the effective capacitance and modified by using the gate-output transition time. The proposed delay calculation halves the error of a conventional rough calculation, achieving a computational error within 10% per gate stage. The mathematical models are simple enough that the method is suitable for quick delay calculation and logic circuit optimization in the early stages of LSI design. A delay optimization tool using this delay calculation method reduced the worst path delay of a multiply-add module by 11.2% and decreased the sizes of 58.1% of the gates.

A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.

Interactions between ESD protection devices and other components of a chip can lead to complex and not easily anticipated discharge bevahior. Triggering of a protection MOSFET is equivalent to the closing of a fast switch and can cause substantial transient discharge currents. The peak value of this current depends on the chip capacitance, resistance, properties of the protection clamp, etc. Careful optimization of the protection circuit is therefore necessary to avoid current overstress and circuit failure.

A mapping circuit in order to have a wider input dynamic range is proposed. MOSFET's connecting between power supply lines are employed to construct the mapping circuit. SPICE simulation is shown to evaluate the proposed circuits. With the proposed mapping circuit, two-MOSFET subtractor has a rail-to-rail input voltage. As an application, an OTA consisting of subtractors is realized by employing the proposed mapping circuits to have a rail-to-rail input voltage range.

A parallel current-mode multilevel identifying circuit for flash memories is proposed. The sensing scheme based on the CMOS cross-coupled structure modified from the clamped bit-line sense amplifier achieves high speed and low power dissipation. The offset of the proposed sense amplifier due to mismatch is also reduced significantly. The circuit has been fabricated using 0.6 µm CMOS technology. The simulation and measurement indicate the sensing speed reaches 1 ns at 3 V supply voltage with average power consumption about 2 mW at 50 MHz.

This paper presents a miniaturized reverse-phase hybrid ring by the use of shunt capacitors, and successfully designs a very miniature hybrid ring of a 0.28-wavelength circumference with a wide bandwidth comparable to the regular reverse-phase hybrid ring based on the equivalent admittance approach. Moreover, a method of broadening the bandwidth with adding a matching network consisting of a very short transmission line and two shunt capacitors at each port is also described. The validity of the proposed design is demonstrated by electromagnetic simulator (Sonnet em) for a uniplanar hybrid ring.

This paper presents a framework for modeling and mixed-mode simulation of circuits/interconnects and electromagnetic (EM-) radiations. The proposed framework investigates the signal integrity in VLSI chips, packages and wiring boards at the GHz-band level, and verifies the electromagnetic interference (EMI) and the electromagnetic compatibility (EMC) of high-speed systems. In our framework, the frequency characteristics of interconnects and EM-radiations are extracted by the full-wave FDTD simulation. The macromodels of interconnects are synthesized as SPICE subcircuits, and the impulse responses of EM-radiations are stored in the database. Once the macromodels are synthesized, the circuit simulation with the consideration of EM-effects can be performed by using SPICE. The EM-field distributions can be also easily calculated by taking convolutions of pre-simulated EM impulse responses and the SPICE results.

In this paper, we propose the CMOS implementation of neuron models for an artificial auditory neural network. We show that when voltage is added directly to the control terminal of the basic circuit of the hardware neuron model, a change in the output firing is observed. Next, based on this circuit, a circuit that changes with time is added to the control terminal of the basic circuit of the hardware neuron model. As a result, a neuron model is constructed with ON firing, adaptation firing, and repetitive firing using CMOS. Furthermore, an improved circuit of a neuron model with OFF firing using CMOS which has been improved from the previous model is also constructed.

This paper introduces a way to realize high-pass, band-stop and all-pass transfer functions using two-integrator loop structure consisting of loss-less and lossy integrators. The basic circuit configuration is constructed with five Operational Transconductance Amplifiers (OTAs) and two grounded capacitors. It is shown that the circuit can realize their circuit transfer functions by choosing the input terminals, and that the circuit parameters can also be independently set by the transconductance gains with the proportional block. Although the basic circuit configuration has been known, it seems that the feature for realizing the high-pass, the band-stop and the all-pass transfer functions makes the structure more attractive and useful. An example is given together with simulated results by PSPICE.

Compatibility of conventional lossless discrete cosine transforms (LDCTs) with the discrete cosine transform (DCT) is not high due to rounding operations. In this paper, we design an LDCT which has high compatibility with the DCT. We first design an 8-point DCT (DCT3) by changing the order of row of the transform matrix and also the way of decomposing the DCT in order to obtain an 8-point LDCT which has high compatibility with the DCT. Next we design an 88-point nonseparable 2D LDCT based on a 4-point lossless Walsh-Hadamard Transform (LWHT) which is multiplier-free. The DCT3 is used, when the nonseparable 2D LDCT is designed. Simulation results show that compatibility of the nonseparable 2D LDCT with the separable 2D DCT is high. We also design an 88-point nonseparable 2D LWHT which is multiplier-free and indicate that its compatibility with the separable 2D Walsh-Hadamard Transform is high.

An efficient algorithm is proposed for finding all solutions of piecewise-linear resistive circuits containing bipolar transistors. This algorithm is based on a powerful test (termed the LP test) for nonexistence of a solution in a given region using linear programming (LP). In the LP test, an LP problem is formulated by surrounding the exponential functions in the Ebers-Moll model by right-angled triangles, and it is solved by LP, for example, by the simplex method. In this paper, it is shown that the LP test can be performed by the dual simplex method, which makes the number of pivotings much smaller. Effectiveness of the proposed technique is confirmed by numerical examples.

This paper deals with a method for designing the driving circuit of an electroluminescent (EL) element whose power consumption is lower and the deviation of output voltage is smaller even when the EL element is replaced with another of a different shape. In this driving circuit, an AC voltage raised by a step-up transformer is supplied to the EL element. The oscillation conditions in the orthodox driving circuits were theoretically analyzed, and a new driving circuit which incorporates these characteristics is proposed. A new prototype driving circuit taking the resonance characteristics between the capacitance of the element and the inductance of the transformer into consideration was made. In the experiment, an inorganic AC EL cable-type element was used as the load of the driving circuit as its impedance can be easily adjusted by changing its length. In comparison with orthodox circuits, the power consumption was lower and the changes in the output voltage were smaller in the new prototype circuit even when the changes in the impedance were large.

We propose herein a motion detection artificial vision model which uses analog electronic circuits. The proposed model is comprised of four layers. The first layer is a differentiation circuit of the large CR coefficient, and the second layer is a differentiation circuit of the small CR coefficient. Thus, the speed of the movement object is detected. The third layer is a difference circuit for detecting the movement direction, and the fourth layer is a multiple circuit for detecting pure motion output. When the object moves from left to right the model outputs a positive signal, and when the object moves from right to left the model outputs a negative signal. We first designed a one-dimensional model, which we later enhanced to obtain a two-dimensional model. The model was shown to be capable of detecting a movement object in the image. Using analog electronic circuits, the number of connections decrease and real-time processing becomes feasible. In addition, the proposed model offers excellent fault tolerance. Moreover, the proposed model can be used to detect two or more objects, which is advantageous for detection in an environment in which several objects are moving in multiple directions simultaneously. Thus, the proposed model allows practical, cheap movement sensors to be realized for applications such as the measurement of road traffic volume or counting the number of pedestrians in an area. From a technological viewpoint, the proposed model facilitates clarification of the mechanism of the biomedical vision system, which should enable design and simulation by an analog electric circuit for detecting the movement and speed of objects.

This paper presents a 0.5Vdd-step pumping method for Dickson-type charge-pump circuits that achieve high overall efficiency, including regulator circuitry, even at large output currents, and these circuits are targeted at mobile equipment applications. We have designed positive and negative charge-pump circuits which use a 0.5Vdd-step pumping method, are implemented with advanced control functions, and are fabricated with our custom CMOS process. Measured results showed that efficiency of a 2.5-stage positive charge-pump circuit before regulation is more than 93% (power supply Vdd=5 V, output voltage Vout=16.9 V 3.5Vdd, output current Iout=4 mA), and that of a 1.5-stage negative charge-pump circuit is 93% (power supply Vdd=5 V, output voltage Vout=-7.2 V -1.5Vdd, output current Iout=4 mA).

In the FDTD simulation of microwave circuits, a device in very small size compared with the wavelength is often handled as a lumped element, but it may still occupy more than one cell instead of a wire structure without volume routinely employed in classical extended FDTD algorithms. In this paper, two modified extended FDTD algorithms incorporating a lumped element occupying more than one cell are developed directly from the integral form of Maxwell's equations based on the assumption whether displacement current exists inside the region where a device is present. If the displacement current exists, the modified extended FDTD algorithm can be represented as a Norton equivalent current-source circuit, or otherwise as a Thevenin equivalent voltage-source circuit. These algorithms are applied in the microwave line loaded by a lumped resistor and an active antenna to illustrated the efficiency and difference of the two algorithms.

An automated synthesis for analog computational circuits in transistor-level configuration is presented. A cell-based structure is introduced to place moderate constraints on the MOSFET circuit topology. Even though each cell has a simple structure that consists of one current path with four transistors, common analog building blocks can be implemented using combinations of the cells. A genetic algorithm is applied to search circuit topologies and transistor sizes that satisfy given specifications. Synthesis capabilities are demonstrated through examples of three types of computational circuits; absolute value, squaring, and cubing functions by using computer simulations and real hardware.

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOSFET (FG-MOSFET) is proposed. First, the grounded VCLVR realization is discussed. The proposed circuit consists of only an ordinary MOSFET and an FG-MOSFET. The advantages of the proposed VCLVR are low-power and wide-input range and also the power consumption of the proposed VCLVR is the same as an ordinary passive resistor. The performance of the proposed circuits are confirmed by HSPICE simulations with a standard 0.6 µm CMOS process parameters. Simulations of the proposed VCLVR demonstrate a resistance value of 40 kΩ to 338 kΩ and an input range of 4.34 V within THD of less than 1.1%. Next, we proposed a new floating node linear variable resistor using the proposed VCLVR. The performance of the circuit is also evaluated through HSPICE.