A High-Speed Current-Mode Multilevel Identifying Circuit for Flash Memories
Summary :
A parallel current-mode multilevel identifying circuit for flash memories is proposed. The sensing scheme based on the CMOS cross-coupled structure modified from the clamped bit-line sense amplifier achieves high speed and low power dissipation. The offset of the proposed sense amplifier due to mismatch is also reduced significantly. The circuit has been fabricated using 0.6 µm CMOS technology. The simulation and measurement indicate the sensing speed reaches 1 ns at 3 V supply voltage with average power consumption about 2 mW at 50 MHz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.2 pp.229-235
- Publication Date
- 2003/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
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Hongchin LIN, Funian LIANG, "A High-Speed Current-Mode Multilevel Identifying Circuit for Flash Memories" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 2, pp. 229-235, February 2003, doi: .
Abstract: A parallel current-mode multilevel identifying circuit for flash memories is proposed. The sensing scheme based on the CMOS cross-coupled structure modified from the clamped bit-line sense amplifier achieves high speed and low power dissipation. The offset of the proposed sense amplifier due to mismatch is also reduced significantly. The circuit has been fabricated using 0.6 µm CMOS technology. The simulation and measurement indicate the sensing speed reaches 1 ns at 3 V supply voltage with average power consumption about 2 mW at 50 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_2_229/_p
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@ARTICLE{e86-c_2_229,
author={Hongchin LIN, Funian LIANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Speed Current-Mode Multilevel Identifying Circuit for Flash Memories},
year={2003},
volume={E86-C},
number={2},
pages={229-235},
abstract={A parallel current-mode multilevel identifying circuit for flash memories is proposed. The sensing scheme based on the CMOS cross-coupled structure modified from the clamped bit-line sense amplifier achieves high speed and low power dissipation. The offset of the proposed sense amplifier due to mismatch is also reduced significantly. The circuit has been fabricated using 0.6 µm CMOS technology. The simulation and measurement indicate the sensing speed reaches 1 ns at 3 V supply voltage with average power consumption about 2 mW at 50 MHz.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A High-Speed Current-Mode Multilevel Identifying Circuit for Flash Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 229
EP - 235
AU - Hongchin LIN
AU - Funian LIANG
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2003
AB - A parallel current-mode multilevel identifying circuit for flash memories is proposed. The sensing scheme based on the CMOS cross-coupled structure modified from the clamped bit-line sense amplifier achieves high speed and low power dissipation. The offset of the proposed sense amplifier due to mismatch is also reduced significantly. The circuit has been fabricated using 0.6 µm CMOS technology. The simulation and measurement indicate the sensing speed reaches 1 ns at 3 V supply voltage with average power consumption about 2 mW at 50 MHz.
ER -
English
