This paper presented a new method to transfer isochronous data through an IEEE 1394 over UWB (ultra wideband) network. The goal of this research is to implement a complete heterogeneous system without commercial IEEE 1394 link chips supporting the bridge-aware function. The method resolving this dedicated chip-less situation, was employed a new bridge adapting a pseudo connection management protocol (CMP). This approach made a wired 1394 devices as an IEEE 1394 over UWB device. This method allowed an IEEE 1394 equipment to transfer an isochronous data using a UWB wireless communication network. The result of this approach was demonstrated successfully via an IEEE 1394 over UWB bridge module. The proposed CMP and IEEE 1394 over UWB bridge module can exchange isochronous data through an IEEE 1394 over UWB network. This method makes an IEEE 1394 equipment transfer an isochronous data using a UWB wireless channel.

In this paper, we propose a simple and accurate method to derive the dwell time distribution of a mobile in a cell by a numerical integration approach. In practical applications, only a few traffic models have a known closed-form solution, most of the models can not be solved in closed form. Therefore a simulation or approximating method has to be used to solve the problems. To validate the accuracy of the proposed method, we apply it to a typical hard handoff traffic model with known closed-form solution and the goodness-of-fit is measured. We also apply this method to a soft handoff traffic model, which does not have a closed-form solution. Computer simulations show promising results based on the non-closed-form application.

A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.

This paper presents a hybrid decimal division algorithm to improve division speed. The proposed hybrid algorithm employs either non-restoring or restoring algorithm on each digit to reduce iterative computations. The selection of the algorithm is based on the relative remainder values with respect to the half of its divisor. The proposed algorithm requires maximum 7n+4 add/subtract operations for an n-digit quotient, whereas other restoring or non-restoring schemes comprise more than 10n+1 operations.