Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design

Norio OHKUBO; Takeo YAMASHITA

Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design

Norio OHKUBO, Takeo YAMASHITA

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An accurate, fast delay calculation method suitable for high-performance, low-power LSI design is proposed. The delay calculation is composed of two steps: (1) the gate delay is calculated by using an effective capacitance obtained from a simple model we propose; and (2) the interconnect delay is also calculated from the effective capacitance and modified by using the gate-output transition time. The proposed delay calculation halves the error of a conventional rough calculation, achieving a computational error within 10% per gate stage. The mathematical models are simple enough that the method is suitable for quick delay calculation and logic circuit optimization in the early stages of LSI design. A delay optimization tool using this delay calculation method reduced the worst path delay of a multiply-add module by 11.2% and decreased the sizes of 58.1% of the gates.

Publication: IEICE TRANSACTIONS on Electronics Vol.E86-C No.4 pp.618-623

Publication Date: 2003/04/01

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Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)

Category: Design Methods and Implementation

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Norio OHKUBO, Takeo YAMASHITA, "Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design" in IEICE TRANSACTIONS on Electronics, vol. E86-C, no. 4, pp. 618-623, April 2003, doi: .
Abstract: An accurate, fast delay calculation method suitable for high-performance, low-power LSI design is proposed. The delay calculation is composed of two steps: (1) the gate delay is calculated by using an effective capacitance obtained from a simple model we propose; and (2) the interconnect delay is also calculated from the effective capacitance and modified by using the gate-output transition time. The proposed delay calculation halves the error of a conventional rough calculation, achieving a computational error within 10% per gate stage. The mathematical models are simple enough that the method is suitable for quick delay calculation and logic circuit optimization in the early stages of LSI design. A delay optimization tool using this delay calculation method reduced the worst path delay of a multiply-add module by 11.2% and decreased the sizes of 58.1% of the gates.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_4_618/_p

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@ARTICLE{e86-c_4_618,
author={Norio OHKUBO, Takeo YAMASHITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design},
year={2003},
volume={E86-C},
number={4},
pages={618-623},
abstract={An accurate, fast delay calculation method suitable for high-performance, low-power LSI design is proposed. The delay calculation is composed of two steps: (1) the gate delay is calculated by using an effective capacitance obtained from a simple model we propose; and (2) the interconnect delay is also calculated from the effective capacitance and modified by using the gate-output transition time. The proposed delay calculation halves the error of a conventional rough calculation, achieving a computational error within 10% per gate stage. The mathematical models are simple enough that the method is suitable for quick delay calculation and logic circuit optimization in the early stages of LSI design. A delay optimization tool using this delay calculation method reduced the worst path delay of a multiply-add module by 11.2% and decreased the sizes of 58.1% of the gates.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 618
EP - 623
AU - Norio OHKUBO
AU - Takeo YAMASHITA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2003
AB - An accurate, fast delay calculation method suitable for high-performance, low-power LSI design is proposed. The delay calculation is composed of two steps: (1) the gate delay is calculated by using an effective capacitance obtained from a simple model we propose; and (2) the interconnect delay is also calculated from the effective capacitance and modified by using the gate-output transition time. The proposed delay calculation halves the error of a conventional rough calculation, achieving a computational error within 10% per gate stage. The mathematical models are simple enough that the method is suitable for quick delay calculation and logic circuit optimization in the early stages of LSI design. A delay optimization tool using this delay calculation method reduced the worst path delay of a multiply-add module by 11.2% and decreased the sizes of 58.1% of the gates.
ER -