This paper proposes an operation-region model for analyzing and testing analog and mixed-signal circuits, which is based on observation of change in MOSFET operation regions. First, the relation between the change in MOSFET operation regions and the fault behavior of a mixed-signal circuit containing a bridging fault is investigated. Next, we propose an analysis procedure based on the operation-region model and apply it to generate the optimal input combination for testing the circuit. We also determine which transistors should be observed in order to estimate the circuit behavior. Since the operation-region model is a method for modeling circuit behavior abstractly, the proposed method will be useful for modeling circuit behavior and for analyzing and testing many kinds of analog and mixed-signal circuits.

In recent years, the domino logic has received much attention as a design technique of high-speed circuits. However, in the case of standard domino logic, only non-inverting functions are allowed. Then, the clock-delayed (CD) domino logic that provides any logic function is proposed in order to overcome such domino's drawback. In addition, domino circuits are more sensitive to circuit noise compared with static CMOS circuits. In particular, crosstalk causes critical problems. Therefore, we focus our attention on crosstalk faults in CD domino circuits. However, in CD domino circuits, there are faults that don't propagate faulty values to any primary output even though crosstalk pulses are generated. Then, we remove such faults from the target fault list by considering structures of CD domino circuits, and perform a fault simulation for the reduced target fault list using two kinds of fault simulation method together. We realize CD domino circuits in VHDL and perform the proposed fault simulation for the combinational part of some benchmark circuits of ISCAS'89 on a VHDL simulator. Fault coverage for random vectors was obtained for s27 to s1494 under the limitation of simulation time.

This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.

The EB tester line delay fault localization algorithm for combinational circuits is proposed where line delay fault probabilities are utilized to narrow fault candidates down to one efficiently. Probabilities for two main causes of line delay faults, defects of contact/vias along interconnections and crosstalk, are estimated through layout analysis. The algorithm was applied to 8 kinds of ISCAS'85 benchmark circuits to evaluate its performance where the guided probe (GP) diagnosis was used as the reference method. The proposed method can cut the number of probed lines to about 30% in average compared with those for the GP method. The total fault localization time was 31% of the time for the GP method and was 6% less than that of our previous method where the fault list generated in concurrent fault simulation is utilized.

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. A new version of parallel EGG system is based on a coarse-grained model of parallel processing and can synthesize heterogeneous networks of various different components efficiently. The potential capability of parallel EGG system is demonstrated through the design of current-mode logic circuits.

A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.

This paper investigates multiple-valued code-division multiple access (MV-CDMA) techniques and circuits for intra/inter-chip communication to achieve efficient data transmission in VLSI systems. To address the problems caused by interconnection complexity, we transmit multiplexed signals inside LSI systems employing pseudo-random orthogonal m-sequences as information carriers. A new class of multiple-valued CDMA techniques for intra-chip communication is discussed to demonstrate the feasibility of eliminating co-channel interference caused by a propagation delay of signals, e.g., clock skew. This paper describes the circuit configuration and performance evaluation of MV-CDMA systems for intra-chip communication. We first explain the principle of MV-CDMA technique, and then propose a bidirectional current-mode CMOS technique to realize compact correlation circuits for CDMA. Finally, we show the Spice and MATLAB simulation results of MV-CDMA systems, which indicate the excellent capabilities of eliminating co-channel interference.

An L-band low quiescent current and low distortion SiGe heterojunction bipolar transistor (HBT) driver amplifier having a self base bias control circuit is described. Since the size of this bias circuit is small and it does not need an external control circuit, it is easy to be integrated with the driver amplifier on a single chip. According to the output power level, the self base bias control circuit, which is the combination of a constant base voltage circuit and p-metal oxide semiconductor (MOS) FET current mirror with a constant current source, automatically controls the base voltage, and allows low quiescent current at low output power level and low distortion at high output power level. The simulated results show that the driver amplifier having the self base bias control circuit achieves 1 dB power compression point (P1 dB) improvement of 2.4 dB compared with the driver amplifier having a conventional constant base voltage under the same quiescent current condition. The fabricated driver amplifier with the proposed bias circuit shows high P1 dB of 15.0 dBm with low quiescent current of 15.3 mA.

This paper presents the full wave analysis of a microwave amplifier by the extended finite difference time domain method. The device-wave interaction is characterized and incorporated into the FDTD time-marching scheme. The equivalent current source is used to model the amplifier and all the electric field components at the active sheet are updated by FDTD. Central-difference approximation is used to discretize a set of state equations. The results obtained by the present method show good agreement with those of the frequency domain circuit analysis and serenade v8.5.

This paper describes a CMOS transponder IC for RFID applications. A full-wave rectifier implemented using NMOS transistors supplies the transponder with a dc supply voltage. A 64-bit ROM has been designed for a data memory. Front-end impedance modulation and Manchester coding are used for transmitting the data from the transponder memory to the reader. A new damping circuit has been proposed and employed for impedance modulation. The designed circuit has been fabricated using a 0.65 µm 2-poly, 2-metal CMOS process. Measurement results show that it has a constant damping rate of around 20-25% and a data transmission rate of 3.9 kbps at a 125 kHz RF carrier. Die area is 0.9 mm0.4 mm. The measured reading distance is up to 7 cm.

The radix-64 encoding scheme was used to reduce the number of partial products in the 5454 CMOS parallel multiplier. The transistor counts, the chip area and the power-delay product were reduced by 28%, 22%, and 17%, respectively, compared to any of the published 5454 CMOS parallel multipliers. A redundant binary (RB) number system was used to represent any of the 65 multiplying coefficients as a RB number which consists of two of 9 fundamental multiplying coefficients and their complements. The resultant RB partial products were added by using optimized RB adders. The total transistor count of the proposed multiplier was 43,579. The chip area in 0.25 µm CMOS process with 5 metal layers was 0.99 mm2. The power consumption and the multiplication time were 111 mW and 6.9 ns, respectively.

A new four-quadrant (4Q) Multiplier complementally using linear and saturation regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is proposed for the wide dynamic range and superior flexibility of the input range. This multiplier operates in the region except for the threshold voltage VT to zero. The validity of the proposed circuit is confirmed through HSPICE simulation.

The transfer characteristic of an integrator is affected by excess-phase shift caused by the parasitic capacitance. The phase compensation is obtained by introducing zeros to generate phase lead. This paper proposes a phase compensation technique for the differential signal input integrator. The proposed technique is employing feedforward signal current source. The fifth-order leapfrog Chebyshev low-pass filter with 0.5 dB passband ripple is designed using the integrator with the proposed phase compensation. Further, an autotuning phase compensation system using the proposed technique is realized by applying a PLL system. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator with the proposed phase compensation shows that excess-phase cancellation is obtained at various unity gain frequencies. The accurate filter characteristic of the fifth-order leapfrog filter is obtained by using the autotuning phase compensation system. The passband of the filter is improved over wide range of frequencies. The proposed technique is suitable for low voltage application.

This paper proposes design of new linear bipolar OTAs using hyperbolic circuits with an intermediate voltage terminal. Four types of the OTAs are presented; two OTAs contain a hyperbolic sine circuit and the other two OTAs employ a hyperbolic cosine circuit. The linear input voltage range of the proposed OTAs is wider than that of the well-known conventional OTA, multi-TANH doublet, while each proposed OTA has advantages, such as low power dissipation, high-frequency characteristics and so on. The results of SPICE simulation show that satisfactory characteristics are obtained.

Digitalization in electronic systems requires the electronics devices in de-coupler sets with low impedance at high frequency, and high reliability. A shield strip type line component with aluminum substrate, its surface oxidized dielectric layer and a conducting polymer electrolyte has been developed. The conducting polymers of polypyrrole and poly(3,4-ethylenedioxythiophene) have been formed by direct chemical oxidative polymerization and electrochemical polymerization on a dielectric layer. Thus, the surface of the dielectric layer is covered with conducting polymer films. The structure of the line component is strip line conformation just like a crushed coaxial cable with in-put and out-put terminals surrounded by the conducting polymer electrolyte. Two types of the components, i.e., a large surface area, 10 20 mm, and a small surface area, 4 4 mm, have been fabricated with polypyrrole and poly(3,4-ethylenedioxythiophene), respectively. The dielectric properties of these line components have been investigated with a Impedance/Gain-phase analyzer and a network analyzer. Due to the high conductivity of the polymer electrolytes, the line components demonstrate low impedance at resonance frequency. Regarding the frequency characteristics of the line components, the impedance and ESR at high frequency are lower than those of the conventional capacitors. Furthermore, the transfer coefficients, S21, are three orders lower than those of other capacitors in a wide frequency band from 10 kHz to 6 GHz. The results indicate the excellent characteristics of the line components for the power line de-coupler set at the boundary of the closed circuit unit.

The characteristics of the Si resonant tunneling metal-oxide-semiconductor transistor (SRTMOST), which has double-barriers at the both edges of the channel, is examined from viewpoints of the substitution for conventional metal-oxide-semiconductor field-effect transistor (MOSFET) in the sub-0.1 µm era. The influence of the double-barriers on the suppression of the drain currents at the gate-off condition is discussed, and the feasibility of the three-valued logic circuit which is composed of the p-MOSFET and the n-SRTMOST is also shown theoretically.

This paper describes a new circuit technique for performing clock recovery and data re-timing functions for high-speed source synchronous data communications, such as in burst-mode data transmission. The new clock recovery circuit is fully digital, non-PLL-based, and is capable of retiming the output clock with the received data within one data transition. The absence of analog filters or other analog blocks makes its area much smaller than conventional circuitry. It can also be described by any hardware description language, simulated, and synthesized into any digital process. This enables it to be ported from one technology to another and support system on a chip (SOC) designs. The design concept is demonstrated with T-Spice(R) simulations using a 0.25 µm digital CMOS technology. Static performance was evaluated in terms of supply and temperature dependent skews. The shifts in output clock due to these static conditions were within 40 pS. Also dynamic behaviours such as jitter generation and jitter transfer were evaluated. The circuit generates a jitter of 68 pS in response to a supply noise of 250 mV amplitude and 100 MHz frequency. Input data jitter transfer is within 0.1 dB up to a jitter frequency of 150 MHz.

This paper describes a radial open stub and its application to a simple design of a four-element planar Butler matrix. In the first stage of our work, we propose a 45-degree phase shifter composed of an eighth-wavelength delay line and a serial connection of a quarter-wavelength straight line and a quarter-wavelength straight open stub. Next, in order to improve relative-phase characteristics between output ports, we propose a 45-degree phase shifter configuration using a quarter-wavelength radial open stub instead of using a quarter-wavelength straight open stub. It is shown by simulation that relative-phase characteristics of the configuration using the radial open stub are better than that using the straight open stub at the high frequencies. Finally, an experimental UHF-band four-element planar Butler matrix is presented. Over the frequency range from 0.83 to 0.92 GHz, the experimental four-element planar Butler matrix exhibits power splits of -6.510.29 dB, return losses of greater than 13 dB, errors in the desired relative-phase difference between output ports of less than 2 degrees.

A new contention-free Domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional Domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 µm CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area were evaluated. At a 3% area increase, and keeping the noise margins constant, the new CF-DOMINO achieves 20% less delay than conventional DOMINO as the threshold voltage scales from 450 mV down to 200 mV. It also achieved 13% less dynamic power and 5% less leakage at that threshold voltage.

At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating trade-off between power and area/delay by applying gated clocks is very important. In this paper, we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks. The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.