Framework of Timed Trace Theoretic Verification Revisited
Summary :
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.
- Publication
- IEICE TRANSACTIONS on Information Vol.E85-D No.10 pp.1595-1604
- Publication Date
- 2002/10/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Test and Verification of VLSI)
- Category
- Verification
Authors
Keyword
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Bin ZHOU, Tomohiro YONEDA, Chris MYERS, "Framework of Timed Trace Theoretic Verification Revisited" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1595-1604, October 2002, doi: .
Abstract: This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1595/_p
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@ARTICLE{e85-d_10_1595,
author={Bin ZHOU, Tomohiro YONEDA, Chris MYERS, },
journal={IEICE TRANSACTIONS on Information},
title={Framework of Timed Trace Theoretic Verification Revisited},
year={2002},
volume={E85-D},
number={10},
pages={1595-1604},
abstract={This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Framework of Timed Trace Theoretic Verification Revisited
T2 - IEICE TRANSACTIONS on Information
SP - 1595
EP - 1604
AU - Bin ZHOU
AU - Tomohiro YONEDA
AU - Chris MYERS
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.
ER -
English
