A Compact Radix-64 54<cd0215f.gif> 54 CMOS Redundant Binary Parallel Multiplier

Sang-Hoon LEE; Seung-Jun BAE; Hong-June PARK

A Compact Radix-64 54 54 CMOS Redundant Binary Parallel Multiplier

Sang-Hoon LEE, Seung-Jun BAE, Hong-June PARK

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The radix-64 encoding scheme was used to reduce the number of partial products in the 5454 CMOS parallel multiplier. The transistor counts, the chip area and the power-delay product were reduced by 28%, 22%, and 17%, respectively, compared to any of the published 5454 CMOS parallel multipliers. A redundant binary (RB) number system was used to represent any of the 65 multiplying coefficients as a RB number which consists of two of 9 fundamental multiplying coefficients and their complements. The resultant RB partial products were added by using optimized RB adders. The total transistor count of the proposed multiplier was 43,579. The chip area in 0.25 µm CMOS process with 5 metal layers was 0.99 mm². The power consumption and the multiplication time were 111 mW and 6.9 ns, respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.6 pp.1342-1350

Publication Date: 2002/06/01

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Type of Manuscript: PAPER

Category: Electronic Circuits

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Sang-Hoon LEE, Seung-Jun BAE, Hong-June PARK, "A Compact Radix-64 54 54 CMOS Redundant Binary Parallel Multiplier" in IEICE TRANSACTIONS on Electronics, vol. E85-C, no. 6, pp. 1342-1350, June 2002, doi: .
Abstract: The radix-64 encoding scheme was used to reduce the number of partial products in the 5454 CMOS parallel multiplier. The transistor counts, the chip area and the power-delay product were reduced by 28%, 22%, and 17%, respectively, compared to any of the published 5454 CMOS parallel multipliers. A redundant binary (RB) number system was used to represent any of the 65 multiplying coefficients as a RB number which consists of two of 9 fundamental multiplying coefficients and their complements. The resultant RB partial products were added by using optimized RB adders. The total transistor count of the proposed multiplier was 43,579. The chip area in 0.25 µm CMOS process with 5 metal layers was 0.99 mm². The power consumption and the multiplication time were 111 mW and 6.9 ns, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_6_1342/_p

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@ARTICLE{e85-c_6_1342,
author={Sang-Hoon LEE, Seung-Jun BAE, Hong-June PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Compact Radix-64 54 54 CMOS Redundant Binary Parallel Multiplier},
year={2002},
volume={E85-C},
number={6},
pages={1342-1350},
abstract={The radix-64 encoding scheme was used to reduce the number of partial products in the 5454 CMOS parallel multiplier. The transistor counts, the chip area and the power-delay product were reduced by 28%, 22%, and 17%, respectively, compared to any of the published 5454 CMOS parallel multipliers. A redundant binary (RB) number system was used to represent any of the 65 multiplying coefficients as a RB number which consists of two of 9 fundamental multiplying coefficients and their complements. The resultant RB partial products were added by using optimized RB adders. The total transistor count of the proposed multiplier was 43,579. The chip area in 0.25 µm CMOS process with 5 metal layers was 0.99 mm². The power consumption and the multiplication time were 111 mW and 6.9 ns, respectively.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A Compact Radix-64 54 54 CMOS Redundant Binary Parallel Multiplier
T2 - IEICE TRANSACTIONS on Electronics
SP - 1342
EP - 1350
AU - Sang-Hoon LEE
AU - Seung-Jun BAE
AU - Hong-June PARK
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2002
AB - The radix-64 encoding scheme was used to reduce the number of partial products in the 5454 CMOS parallel multiplier. The transistor counts, the chip area and the power-delay product were reduced by 28%, 22%, and 17%, respectively, compared to any of the published 5454 CMOS parallel multipliers. A redundant binary (RB) number system was used to represent any of the 65 multiplying coefficients as a RB number which consists of two of 9 fundamental multiplying coefficients and their complements. The resultant RB partial products were added by using optimized RB adders. The total transistor count of the proposed multiplier was 43,579. The chip area in 0.25 µm CMOS process with 5 metal layers was 0.99 mm². The power consumption and the multiplication time were 111 mW and 6.9 ns, respectively.
ER -