Silicon Resonant Tunneling Metal-Oxide-Semiconductor Transistor for Sub-0.1 µm Era
Summary :
The characteristics of the Si resonant tunneling metal-oxide-semiconductor transistor (SRTMOST), which has double-barriers at the both edges of the channel, is examined from viewpoints of the substitution for conventional metal-oxide-semiconductor field-effect transistor (MOSFET) in the sub-0.1 µm era. The influence of the double-barriers on the suppression of the drain currents at the gate-off condition is discussed, and the feasibility of the three-valued logic circuit which is composed of the p-MOSFET and the n-SRTMOST is also shown theoretically.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E85-C No.5 pp.1086-1090
- Publication Date
- 2002/05/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices)
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Naoto MATSUO, Yoshinori TAKAMI, Takahiro NOZAKI, Hiroki HAMADA, "Silicon Resonant Tunneling Metal-Oxide-Semiconductor Transistor for Sub-0.1 µm Era" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1086-1090, May 2002, doi: .
Abstract: The characteristics of the Si resonant tunneling metal-oxide-semiconductor transistor (SRTMOST), which has double-barriers at the both edges of the channel, is examined from viewpoints of the substitution for conventional metal-oxide-semiconductor field-effect transistor (MOSFET) in the sub-0.1 µm era. The influence of the double-barriers on the suppression of the drain currents at the gate-off condition is discussed, and the feasibility of the three-valued logic circuit which is composed of the p-MOSFET and the n-SRTMOST is also shown theoretically.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1086/_p
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@ARTICLE{e85-c_5_1086,
author={Naoto MATSUO, Yoshinori TAKAMI, Takahiro NOZAKI, Hiroki HAMADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Silicon Resonant Tunneling Metal-Oxide-Semiconductor Transistor for Sub-0.1 µm Era},
year={2002},
volume={E85-C},
number={5},
pages={1086-1090},
abstract={The characteristics of the Si resonant tunneling metal-oxide-semiconductor transistor (SRTMOST), which has double-barriers at the both edges of the channel, is examined from viewpoints of the substitution for conventional metal-oxide-semiconductor field-effect transistor (MOSFET) in the sub-0.1 µm era. The influence of the double-barriers on the suppression of the drain currents at the gate-off condition is discussed, and the feasibility of the three-valued logic circuit which is composed of the p-MOSFET and the n-SRTMOST is also shown theoretically.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Silicon Resonant Tunneling Metal-Oxide-Semiconductor Transistor for Sub-0.1 µm Era
T2 - IEICE TRANSACTIONS on Electronics
SP - 1086
EP - 1090
AU - Naoto MATSUO
AU - Yoshinori TAKAMI
AU - Takahiro NOZAKI
AU - Hiroki HAMADA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - The characteristics of the Si resonant tunneling metal-oxide-semiconductor transistor (SRTMOST), which has double-barriers at the both edges of the channel, is examined from viewpoints of the substitution for conventional metal-oxide-semiconductor field-effect transistor (MOSFET) in the sub-0.1 µm era. The influence of the double-barriers on the suppression of the drain currents at the gate-off condition is discussed, and the feasibility of the three-valued logic circuit which is composed of the p-MOSFET and the n-SRTMOST is also shown theoretically.
ER -
English
