IEICE TRANSACTIONS on Electronics
A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
Summary :
A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E85-C No.8 pp.1625-1633
- Publication Date
- 2002/08/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Optoelectronics
Authors
Satoru HANZAWA
Hiromasa NODA
Takeshi SAKATA
Osamu NAGASHIMA
Sadayuki MORITA
Masanori ISODA
Michiyo SUZUKI
Sadayuki OHKUMA
Kyoko MURAKAMI
Keyword
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Satoru HANZAWA, Hiromasa NODA, Takeshi SAKATA, Osamu NAGASHIMA, Sadayuki MORITA, Masanori ISODA, Michiyo SUZUKI, Sadayuki OHKUMA, Kyoko MURAKAMI, "A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 8, pp. 1625-1633, August 2002, doi: .
Abstract: A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_8_1625/_p
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@ARTICLE{e85-c_8_1625,
author={Satoru HANZAWA, Hiromasa NODA, Takeshi SAKATA, Osamu NAGASHIMA, Sadayuki MORITA, Masanori ISODA, Michiyo SUZUKI, Sadayuki OHKUMA, Kyoko MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs},
year={2002},
volume={E85-C},
number={8},
pages={1625-1633},
abstract={A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1625
EP - 1633
AU - Satoru HANZAWA
AU - Hiromasa NODA
AU - Takeshi SAKATA
AU - Osamu NAGASHIMA
AU - Sadayuki MORITA
AU - Masanori ISODA
AU - Michiyo SUZUKI
AU - Sadayuki OHKUMA
AU - Kyoko MURAKAMI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2002
AB - A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.
ER -
English
