In this paper we present a method to generate test sequences for stuck-at faults in sequential circuits which have distinguishing sequences. Since the circuit may have no distinguishing sequence, we use two design techniques for circuits which have distinguishing sequences. One is at state transition level and the other is at gate level. In our proposed method complete test sequence can be generated. The sequence consists of test vectors for the combinational part of the circuit, distinguishing sequences and transition sequences. The test vectors, which are generated by a combinational test generator, cause faulty staes or faulty output responses for a fault, and disinguishing sequences identify the differences between faulty states and fault free states. Transition sequences are necessary to make the state in the combinational vectors. And the distinguishing sequence and the transition sequence are used in the initializing sequence. Some techniques for shortening the test sequence is also proposed. The basic ideas of the techniques are to use a short initializing sequence and to find the order in concatenating sequences. But fault simulation is conducted so as not to miss any faults. The initializing sequence is obtained by using a distinguishing sequence. The efficiency of our method is shown in the experimental results for benchmark circuits.

The efficiency of a guided-probe fault location process is affected by the number of the probed lines. This number depends on the size of the target area and the method by which a line is selected for probing. This paper presents a method for reducing the size of the target area in a sequential circuit by introducing the concepts of Type- and Type- faults. This paper also presents a method of selecting lines for probing in a more efficient way. The efficiency of the proposed methods is demonstrated by experimental results.

This paper presents the concept of k-FR circuits. The controllability of such a circuit is high due to its special structure. It is shown that all stuck-at faults and stuck-open faults in a k-FR circuit can be detected and located by k(k1)1 test vectors under the highly observable condition which assumes the output of every gate to be observable. k is usually two or three. This paper also presents an algorithm for converting an arbitrary combinational circuit into a k-FR circuit. A k-FR circuit is easy to test when using technologies such as the electron-beam probing, the current measurement, or the CrossCheck testability solution.

Robust test has been proposed to overcome the potential invalidation of the two-patten test due to hazards. However, it is difficult to generate robust test patterns and they may not exist for some stuck-open faults. In this paper, to overcome this difficulty, we propose a new testable design method with the robustness. Since a faulty gate is regarded as a tri-state element, the gate output node can be set to arbitrary logic value from the outside of a circuit. In the proposed method, on the basis of this idea, each output of the gate can be set to any logic value by an extra driver. Then, it is checked what value the output gives. Any stuck-open fault can be detected by one test pattern by this method which can be implemented relatively easily. To reduce the number of observalbe points, we also consider a method for selecting internal observable points without losing the property of the robustness. As a result, output nodes of reconvergent gates are used as internal observable points. Experimental results of the pattern generation for some benchmark circuits are given.

In this paper, we propose a method, called PORT-D, for optimizing CMOS logic circuits to reduce the average power dissipation. PORT-D is an extensional method of PORT. While PORT reduces the average power dissipation under the zero delay model, PORT-D reduces the average power dissipation by taking into account of the gate delay. In PORT-D, the average power dissipation is estimated by the revised BDD traversal method. The revised BDD traversal method calculates switching activity of gate output by constructing OBDD's without representing switching condition of a gate output. PORT-D modifies the circuit in order to reduce the average power dissipation, where transformations which reduce the average power dissipation are found by using permissible functions. Experimental results for benchmark circuits show PORT-D reduces the average power dissipation more than the number of transistors. Furthermore, we modify PORT-D to have high power reduction capability. In the revised method, named PORT-MIX, a mixture strategy of PORT and PORT-D is implemented. Experimental results show PORT-MIX has higher power reduction capability and higher area optimization capability than PORT-D.

This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.

This paper presents a new methodology for diagnosing transistor leakage faults in a CMOS circuit by using both IDDQ and logic value information. A hierarchical procedure is used to identify and delete impossible fault candidates efficiently and a procedure is employed to generate diagnostic tests for improving diagnostic resolution. A novel approach for handling the intermediate output voltage of a faulty gate is used in new methods for fault simulation and diagnostic test generation based on primary output values. Experimental results on ISCAS85 circuits show the effectiveness of the proposed methodology.

The logic optimization based on redundancy addition and removal is one of methods which can deal with large-scale logic circuits. In this logic optimization a few redundant elements are added to a logic circuit, and then many other redundant elements which are generated by the redundancy addition are identified and removed. In this paper an optimization method based on redundancy addition and removal using implication relations is proposed. The advantage of the proposed method is to identify removable redundant elements with short time, because the proposed method directly identifies redundant elements using implication relations from two illegal signal assignments which are produced by redundancy addition. The experimental results compared this method with another method show that this method is faster than the another method without declining the optimization ability.

In this paper, we analyze the throughput of the Stop-and-wait and Go-back-N ARQ schemes over an unreliable channel modeled by the two-state Markov process. Generally, in these states, block error probabilities are different. From analytical results and numerical examples, we show that the throughput of the Stop-and-wait ARQ scheme only depends on overall average error probability, while that of the Go-back-N ARQ scheme depends on the characteristic of the Markov process.

To speed up a guided-probe diagnosis process, the number of probed lines needs to be reduced. This paper presents two efficient probing line determination methods by which the number of probed lines is either small or minimum. The concept of fault probability is introduced to reflect the fact that not all gates have the same probability to be faulty. Experimental results show the effectiveness of the proposed methods.

In recent years, the domino logic has received much attention as a design technique of high-speed circuits. However, in the case of standard domino logic, only non-inverting functions are allowed. Then, the clock-delayed (CD) domino logic that provides any logic function is proposed in order to overcome such domino's drawback. In addition, domino circuits are more sensitive to circuit noise compared with static CMOS circuits. In particular, crosstalk causes critical problems. Therefore, we focus our attention on crosstalk faults in CD domino circuits. However, in CD domino circuits, there are faults that don't propagate faulty values to any primary output even though crosstalk pulses are generated. Then, we remove such faults from the target fault list by considering structures of CD domino circuits, and perform a fault simulation for the reduced target fault list using two kinds of fault simulation method together. We realize CD domino circuits in VHDL and perform the proposed fault simulation for the combinational part of some benchmark circuits of ISCAS'89 on a VHDL simulator. Fault coverage for random vectors was obtained for s27 to s1494 under the limitation of simulation time.

Retiming is a technique to resynthesize a synchronous sequential circuit by rearranging flip-flops. In view of logic optimization, retiming can potentially derive a circuit which is more simplified and testable because retiming can convert several sequential redundancies into combinational redundancies. Retiming methods proposed before have no guarantee to generate the same output sequences when the circuit start from a specified initial state such as the reset state. If the circuit with a specified initial state must have the same output sequences after retiming, rearrangement of flip-flops should be restricted. This paper presents a retiming method for circuits with a specified initial state so that retimed circuits give the same output sequences of the original circuits for any input sequences. In the proposed method, during the procedure of retiming each flip-flop keeps a value corresponding to the initial state and unification of flip-flops with different value is avoided. Our procedures uses 5-valued logic on gate level implementation to describe and calculate the values of flip-flops. Therefore after optimization using our method, the circuit has completely the same behavior as that of the original. Experimental results for ISCAS'89 benchmark circuits show the method can be used to optimize the circuits as well as a method without considering the initial state. And testability of the retimed circuit is more enhanced than that of the original circuit.

In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.

This paper proposes a new per-test fault diagnosis method based on the X-fault model. The X-fault model can represent all possible faulty behaviors of a physical defect or defects in a gate and/or on its fanout branches by assigning different X symbols assigned to the fanout branches. A partial symbolic fault simulation method is proposed for the X-fault model. Then, a novel technique is proposed for extracting more diagnostic information by analyzing matching details between observed and simulated responses. Furthermore, a unique method is proposed to score the results of fault diagnosis. Experimental results on benchmark circuits demonstrate the superiority of the proposed method over conventional per-test fault diagnosis based on the stuck-at fault model.

Static learning is a procedure to extract implication relations of a logic circuit. In this paper we point out that the number of the extracted implication relations by static learning depends on the order of signal lines processed. Also, we show four procedures for ordering signal lines processed and the effectiveness of the ordering procedures by experiments.

In high-speed packet networks, protocol processing overhead time becomes remarkable in determining the system performance. In this paper, we present a new Selective-Repeat ARQ scheme (called Block SR-ARQ sheme), in which a packet is transmitted or retransmitted in the same way as basic SR-ARQ scheme, but a single acknowledgement packet is used to acknowledge a block of packets. The maximum number of packets acknowledged by an acknowledgement packet is defined as block size. We analyze the system throughput and the average packet delay over the system, and the accuracy of approximately analyzed results is validated by simulation. Furthermore, we show that there exists an optimal block size which obtains both the maximum throughput and the minimum average packet delay.

With the scale-down of VLSI chip size and the reduction of switching time of logic gates, crosstalk faults become an important problem in testing of VLSI. For synchronous sequential circuits, the crosstalk pulses on data lines will be considered to be harmless, because they can be invalidated by a clocking phase. However, crosstalk pulses generated on clock lines or reset lines will cause an erroneous operation. In this work, we have analyzed a crosstalk fault scheme, and developed a fault simulator based on the scheme. Throughout this work, we considered the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in addition to a logic value, the unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates vary widely depending on circuit characteristics. Fault detection rates of up to 80% are obtained from our simulation with test vectors generated at random.

Open faults are difficult to test since the voltage at the floating line is unpredictable and depends on the voltage at the adjacent lines. The effect of open faults can be easily excited if a test pattern provides the opposite logic value to most of the adjacent lines. In this paper, we present a procedure to generate as high a quality test as possible. We define the test quality for evaluating the effect of adjacent lines by assigning an opposite logic value to the faulty line. In our proposed test generation method, we utilize the SAT-based ATPG method. We generate test patterns that propagate the faulty effect to primary outputs and assign logic values to adjacent lines opposite that of the faulty line. In order to estimate test quality for open faults, we define the excitation effectiveness Eeff. To reduce the test volume, we utilize the open fault simulation. We calculate the excitation effectiveness by open fault simulation in order to eliminate unnecessary test patterns. The experimental results for the benchmark circuits prove the effectiveness of our procedure.

This paper presents a novel approach to improving the IDDQ-based diagnosability of a CMOS circuit by dividing the circuit into independent partitions and using a separate power supply for each partition. This technique makes it possible to implement multiple IDDQ measurement points, resulting in improved IDDQ-based diagnosability. The paper formalizes the problem of partitioning a circuit for this purpose and proposes optimal and heuristic based solutions. The effectiveness of the proposed approach is demonstrated through experimental results.